From 4562c61af3b112ba5296f6f6b51b6c97737c8c63 Mon Sep 17 00:00:00 2001
From: Teo Ene <teodor@rivendell.ecen.okstate.edu>
Date: Wed, 3 Mar 2021 15:20:38 -0600
Subject: [PATCH] Fix to last push
---
wally-pipelined/testbench/testbench-coremark.sv | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv
index 4aef5e408..9f458567a 100644
--- a/wally-pipelined/testbench/testbench-coremark.sv
+++ b/wally-pipelined/testbench/testbench-coremark.sv
@@ -32,7 +32,6 @@ module testbench();
logic [`XLEN-1:0] signature[0:10000];
logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
- logic [31:0] InstrW;
logic [`XLEN-1:0] meminit;
string tests[];
logic [`AHBW-1:0] HRDATAEXT;
@@ -62,9 +61,10 @@ module testbench();
wallypipelinedsoc dut(.*);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
+ dut.hart.ifu.InstrF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
- dut.hart.ifu.InstrM, InstrW,
- InstrDName, InstrEName, InstrMName, InstrWName);
+ dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
+ InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
initial
begin
@@ -86,13 +86,13 @@ endmodule
/* verilator lint_on WIDTH */
module instrTrackerTB(
input logic clk, reset, FlushE,
- input logic [31:0] InstrD,
+ input logic [31:0] InstrF, InstrD,
input logic [31:0] InstrE, InstrM,
- output logic [31:0] InstrW,
- output string InstrDName, InstrEName, InstrMName, InstrWName);
+ input logic [31:0] InstrW,
+ output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// stage Instr to Writeback for visualization
- flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
+ instrNameDecTB fdec(InstrF, InstrFName);
instrNameDecTB ddec(InstrD, InstrDName);
instrNameDecTB edec(InstrE, InstrEName);
instrNameDecTB mdec(InstrM, InstrMName);