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Merge pull request #965 from davidharrishmc/dev

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Fixed VCS lockstep simulation with RV32GC config
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Rose Thompson 2024-09-26 10:26:36 -05:00 committed by GitHub
commit 44db028b9e
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3 changed files with 8 additions and 7 deletions
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11
bin/wsim
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@ -86,11 +86,12 @@ if (args.tb == "testbench_fp"):
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if((args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp) and args.sim == "questa"):
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
prefix = "MTI_VCO_MODE=64 " + prefix
else:
prefix = ""
prefix = ""
if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
if (args.sim == "questa" or args.sim == "vcs"):
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
if (args.sim == "questa"):
prefix = "MTI_VCO_MODE=64 " + prefix
if (args.lockstep or args.lockstepverbose):
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)

3
config/rv64gc/coverage.svh
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@ -7,5 +7,6 @@
`include "RV64I_coverage.svh"
`include "RV64M_coverage.svh"
//`include "RV64F_coverage.svh"
`include "RV64F_coverage.svh"
`include "RV64Zicond_coverage.svh"
`include "RV64Zca_coverage.svh"

1
src/ieu/alu.sv
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@ -98,7 +98,6 @@ module alu import cvw::*; #(parameter cvw_t P) (
3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt
3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu
3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
// 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported)
3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
3'b111: FullResult = AndResult; // and, bclr, czero.*