diff --git a/bin/wsim b/bin/wsim
index 88b0dd6c8..38213a332 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -86,11 +86,12 @@ if (args.tb == "testbench_fp"):
 # if lockstep is enabled, then we need to pass the Imperas lockstep arguments
 if(int(args.locksteplog) >= 1): EnableLog = 1
 else: EnableLog = 0
-if((args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp) and args.sim == "questa"):
-    prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
-    prefix = "MTI_VCO_MODE=64 " + prefix
-else:
-    prefix = ""
+prefix = ""
+if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
+   if (args.sim == "questa" or args.sim == "vcs"):
+        prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
+   if (args.sim == "questa"):
+        prefix = "MTI_VCO_MODE=64 " + prefix
 
 if (args.lockstep or args.lockstepverbose):
     if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) 
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
index 855c1f6a9..c89b116c9 100644
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@@ -7,5 +7,6 @@
 
 `include "RV64I_coverage.svh"
 `include "RV64M_coverage.svh"
-//`include "RV64F_coverage.svh"
+`include "RV64F_coverage.svh"
 `include "RV64Zicond_coverage.svh"
+`include "RV64Zca_coverage.svh"
diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index acd5b025d..b63123126 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -98,7 +98,6 @@ module alu import cvw::*; #(parameter cvw_t P) (
       3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT};       // slt
       3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU};      // sltu
       3'b100: FullResult = A ^ CondMaskInvB;               // xor, xnor, binv
-//      3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported)
       3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
       3'b110: FullResult = A | CondMaskInvB;               // or, orn, bset
       3'b111: FullResult = AndResult;                      // and, bclr, czero.*