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Update IR to make synth happy

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Matthew 2024-06-26 22:59:07 -05:00
parent 1c58b20cea
commit 44335fdac9
1 changed files with 1 additions and 1 deletions
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src/debug/ir.sv
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@ -71,7 +71,7 @@ module ir (
always @(posedge updateIR or negedge resetn) begin always @(posedge updateIR or negedge resetn) begin
if (~resetn) if (~resetn)
{BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100; {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100;
else if (updateIR) else
{BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded; {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded;
end end
/* verilator lint_on SYNCASYNCNET */ /* verilator lint_on SYNCASYNCNET */