From 44335fdac9f9d3381371d038793eafcb12053329 Mon Sep 17 00:00:00 2001
From: Matthew <106996253+Matthew-Otto@users.noreply.github.com>
Date: Wed, 26 Jun 2024 22:59:07 -0500
Subject: [PATCH] Update IR to make synth happy

---
 src/debug/ir.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/debug/ir.sv b/src/debug/ir.sv
index 6c5f80b6e..60fd2365f 100644
--- a/src/debug/ir.sv
+++ b/src/debug/ir.sv
@@ -71,7 +71,7 @@ module ir (
   always @(posedge updateIR or negedge resetn) begin
     if (~resetn)
       {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100;
-    else if (updateIR)
+    else
       {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded;
   end
   /* verilator lint_on SYNCASYNCNET */