From 434d6b2c5c949611e7cc5bc14a1775d4dd0f2b9d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 15 Oct 2023 06:41:52 -0700 Subject: [PATCH] minfo test working again with mconfigptr for RV64 --- sim/Makefile | 1 + sim/imperas.ic | 8 +++++++- sim/sim-wally | 2 +- src/ieu/alu.sv | 2 ++ src/privileged/csrm.sv | 2 +- tests/riscof/sail_cSim/riscof_sail_cSim.py | 2 ++ tests/riscof/spike/riscof_spike.py | 2 ++ .../privilege/references/WALLY-minfo-01.reference_output | 4 ++++ .../rv64i_m/privilege/src/WALLY-minfo-01.S | 4 ++-- 9 files changed, 22 insertions(+), 5 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index ac37a36b7..52f7efdcf 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -49,6 +49,7 @@ clean: riscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions make -C ../tests/riscof/ + memfiles: make -f makefile-memfile wally-sim-files --jobs diff --git a/sim/imperas.ic b/sim/imperas.ic index 8ac8dd64e..0afb81c10 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -14,8 +14,14 @@ --override cpu/add_implicit_Extensions=B --override cpu/bitmanip_version=1.0.0 -# ???? +# More extensions --override cpu/Zicbom=T +--override cpu/Zicbop=T +--override cpu/Zicboz=T +--override cpu/Svpbmt=T +# 64 KiB continuous huge pages supported +--override cpu/Svnapot_page_mask=1<<16 + # clarify #--override refRoot/cpu/mtvec_sext=F diff --git a/sim/sim-wally b/sim/sim-wally index 410cc5406..6ffc3ca4f 100755 --- a/sim/sim-wally +++ b/sim/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally.do rv64gc arch64d" +vsim -do "do wally.do rv64gc wally64priv" diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 1906c85e5..55946a411 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -51,6 +51,8 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( logic Asign, Bsign; // Sign bits of A, B // Addition + // CondMaskB is B for add/sub, or a masked version of B for certain bit manipulation instructions + // CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index ad1f9b75d..6e5a49c80 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -145,7 +145,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN); assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT); - assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); + assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID | CSRAdrM == MCONFIGPTR); // CSRs flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 972b838e1..1a6c72504 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -57,6 +57,8 @@ class sail_cSim(pluginTemplate): self.isa += 'i' if "M" in ispec["ISA"]: self.isa += 'm' + if "A" in ispec["ISA"]: + self.isa += 'a' if "C" in ispec["ISA"]: self.isa += 'c' if "F" in ispec["ISA"]: diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 4a5b68b96..1f4a4b838 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -99,6 +99,8 @@ class spike(pluginTemplate): self.isa += 'i' if "M" in ispec["ISA"]: self.isa += 'm' + if "A" in ispec["ISA"]: + self.isa += 'a' if "F" in ispec["ISA"]: self.isa += 'f' if "D" in ispec["ISA"]: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output index 455ff77ed..d38ddb879 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output @@ -14,5 +14,9 @@ 00000000 00000011 # confirm read-only permissions of mhartid 00000000 +00000002 # write to read-only CSR failed with illegal instruction +00000000 +00000011 # confirm read-only permissions of mconfigptr +00000000 0000000b # ecall from terminating tests in M mode 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index f7e183ba7..195f290a8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo) INIT_TESTS @@ -34,7 +34,7 @@ CSR_R_ACCESS mvendorid CSR_R_ACCESS marchid CSR_R_ACCESS mimpid CSR_R_ACCESS mhartid -# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22 +CSR_R_ACCESS mconfigptr END_TESTS