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https://github.com/openhwgroup/cvw
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uncore cleanup
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@ -5,6 +5,8 @@
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//
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// Purpose: AHB to APB bridge
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//
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// Documentation: RISC-V System on Chip Design Chapter 6
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -7,6 +7,8 @@
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// Purpose: Core-Local Interruptor
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// See FE310-G002-Manual-v19p05 for specifications
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -8,6 +8,8 @@
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// See FE310-G002-Manual-v19p05 for specifications
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// No interrupts, drive strength, or pull-ups supported
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -9,6 +9,8 @@
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// With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
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// Supports only 1 target core and only a global threshold.
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// *** Big questions:
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// Do we detect requests as level-triggered or edge-trigged?
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// If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests?
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@ -6,6 +6,8 @@
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//
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// Purpose: On-chip RAM, external to core, with AHB interface
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//
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// Documentation: RISC-V System on Chip Design Chapter 6
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -6,6 +6,8 @@
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//
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// Purpose: On-chip ROM, external to core
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//
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// Documentation: RISC-V System on Chip Design Chapter 6
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -28,44 +28,44 @@
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`define SDCCLKDIV -8'd3
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module SDC
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(input logic HCLK,
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input logic HRESETn,
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input logic HSELSDC,
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input logic [4:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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output logic [`XLEN-1:0] HREADSDC,
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output logic HRESPSDC,
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output logic HREADYSDC,
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module SDC (
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input logic HCLK,
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input logic HRESETn,
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input logic HSELSDC,
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input logic [4:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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output logic [`XLEN-1:0] HREADSDC,
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output logic HRESPSDC,
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output logic HREADYSDC,
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//sd card interface
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// place the tristate drivers at the top. this level
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// will use dedicated 1 direction ports.
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output logic SDCCmdOut,
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input logic SDCCmdIn,
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output logic SDCCmdOE,
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input logic [3:0] SDCDatIn,
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output logic SDCCLK,
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//sd card interface
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// place the tristate drivers at the top. this level
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// will use dedicated 1 direction ports.
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output logic SDCCmdOut,
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input logic SDCCmdIn,
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output logic SDCCmdOE,
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input logic [3:0] SDCDatIn,
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output logic SDCCLK,
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// interrupt to PLIC
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output logic SDCIntM
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);
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// interrupt to PLIC
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output logic SDCIntM);
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logic InitTrans;
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logic RegRead;
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logic RegWrite;
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logic [4:0] HADDRDelay;
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logic InitTrans;
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logic RegRead;
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logic RegWrite;
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logic [4:0] HADDRDelay;
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// Register outputs
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logic signed [7:0] CLKDiv;
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logic [2:0] Command;
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logic [63:9] Address;
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logic signed [7:0] CLKDiv;
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logic [2:0] Command;
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logic [63:9] Address;
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logic SDCDone;
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logic SDCDone;
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logic [2:0] ErrorCode;
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logic InvalidCommand;
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@ -27,14 +27,14 @@
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`include "wally-config.vh"
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module SDCcounter #(parameter integer WIDTH=32)
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(
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input logic [WIDTH-1:0] CountIn,
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output logic [WIDTH-1:0] CountOut,
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input logic Load,
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input logic Enable,
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input logic clk,
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input logic reset);
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module SDCcounter #(parameter integer WIDTH=32) (
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input logic [WIDTH-1:0] CountIn,
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output logic [WIDTH-1:0] CountOut,
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input logic Load,
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input logic Enable,
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input logic clk,
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input logic reset
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);
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logic [WIDTH-1:0] NextCount;
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@ -27,8 +27,7 @@
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`include "wally-config.vh"
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module clkdivider #(parameter integer g_COUNT_WIDTH)
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(
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module clkdivider #(parameter integer g_COUNT_WIDTH) (
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input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX, //((Divide by value)/2) - 1
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input logic i_EN, //Enable frequency division of i_clk
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input logic i_CLK, // 1.2 GHz Base clock
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@ -36,7 +35,7 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
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// i_RST must NOT be a_RST, it needs to be synchronized with the 50 MHz Clock to load the
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// counter's initial value
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output logic o_CLK // frequency divided clock
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);
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);
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logic [g_COUNT_WIDTH-1:0] r_count_out; // wider for sign
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@ -28,12 +28,13 @@
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`include "wally-config.vh"
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module crc16_sipo_np_ce
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(input logic CLK, // sequential device
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input logic RST, // initial calue of CRC register must be "0000_0000_0000_0000"
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input logic i_enable, // input is valid
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input logic i_message_bit,
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output logic [15:0] o_crc16);
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module crc16_sipo_np_ce(
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input logic CLK, // sequential device
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input logic RST, // initial calue of CRC register must be "0000_0000_0000_0000"
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input logic i_enable, // input is valid
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input logic i_message_bit,
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output logic [15:0] o_crc16
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);
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logic [15:0] w_crc16_d;
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@ -29,12 +29,13 @@
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`include "wally-config.vh"
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module crc7_pipo
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(input logic [39:0] i_DATA,
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input logic i_CRC_ENABLE,
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input logic RST,
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input logic CLK,
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output logic [6:0] o_CRC);
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module crc7_pipo (
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input logic [39:0] i_DATA,
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input logic i_CRC_ENABLE,
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input logic RST,
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input logic CLK,
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output logic [6:0] o_CRC
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);
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logic [6:0] r_lfsr_q;
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logic [6:0] w_lfsr_d;
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`include "wally-config.vh"
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module crc7_sipo_np_ce
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(
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input logic clk,
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input logic rst,// initial CRC value must be b"000_0000"
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input logic i_enable,
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input logic i_message_bit,
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output logic [6:0] o_crc7);
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module crc7_sipo_np_ce(
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input logic clk,
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input logic rst,// initial CRC value must be b"000_0000"
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input logic i_enable,
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input logic i_message_bit,
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output logic [6:0] o_crc7
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);
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logic [6:0] w_crc7_d;
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@ -25,17 +25,16 @@
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`include "wally-config.vh"
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module piso_generic_ce #(parameter integer g_BUS_WIDTH)
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(
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input logic clk,
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input logic i_load,
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input logic [g_BUS_WIDTH-1:0] i_data,
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input logic i_en,
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output o_data);
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module piso_generic_ce #(parameter integer g_BUS_WIDTH) (
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input logic clk,
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input logic i_load,
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input logic [g_BUS_WIDTH-1:0] i_data,
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input logic i_en,
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output o_data);
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logic [g_BUS_WIDTH-1:0] w_reg_d;
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logic [g_BUS_WIDTH-1:0] r_reg_q;
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logic [g_BUS_WIDTH-1:0] w_reg_d;
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logic [g_BUS_WIDTH-1:0] r_reg_q;
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flopenr #(g_BUS_WIDTH)
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shiftReg(.clk(clk),
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@ -1,55 +0,0 @@
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SD Flash interface
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regsiter map:
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1. clock divider
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2. address
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3. data register
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4. command register
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5. size register
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Number of bytes to read or write.
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6. status register
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1. bits 11 to 0: bytes currently in the buffer
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2. bits 12 to 29: reservered
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3. bit 30: fault
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4. bit 31: busy
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5. bits XLEN-1 to 32: reservered
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non dma read operation
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1. write the address regsiter
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2. write the command register to read
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3. wait for interrupt or pool on status
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4. Check status for fault and number of bytes.
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5. read the data register for 512 bytes. (64 ld, or 128 lw)
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non dma write operation
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1. write address register
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2. write data register for 512 bytes. (64 sd, or 128 sw)
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3. write command register to write data to flash
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4. wait for interrupt or pool on status
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5. check status for fault and number of bytes written.
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implement dma transfers later
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interrupts
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1. operation done
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2. bus error (more of an exception)
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Occurs if attempting to do an operation while the flash controller is busy.
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ie. if status[31] is set generate an interrupt
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This is tricky in a multiprocessor environment.
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tasks
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1. [-] Remove all AFRL identifiers
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2. [X] get the existing sdc compiled on wally.
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1. [X] use wally primatives over tcore's
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3. build abhlite interface with the above registers and necessary fsm.
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1. [ ] The sd card reader uses a 4 bit data interface. We can change this to be something
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more pratical.
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4. write test programs
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5. [X] Convert VHDL to system verilog
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@ -25,14 +25,15 @@
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`include "wally-config.vh"
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module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
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(input logic clk,
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input logic we1,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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output logic [(2**DEPTH)*WIDTH-1:0] Rd1All,
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input logic [DEPTH-1:0] wa1,
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input logic [WIDTH-1:0] wd1);
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module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4) (
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input logic clk,
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input logic we1,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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output logic [(2**DEPTH)*WIDTH-1:0] Rd1All,
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input logic [DEPTH-1:0] wa1,
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input logic [WIDTH-1:0] wd1
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);
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logic [WIDTH-1:0] regs [2**DEPTH-1:0];
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genvar index;
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@ -25,14 +25,15 @@
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`include "wally-config.vh"
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module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
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(input logic clk,
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input logic we1,
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input logic [WIDTH-1:0] we1bit,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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input logic [DEPTH-1:0] wa1,
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input logic [WIDTH-1:0] wd1);
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module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)(
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input logic clk,
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input logic we1,
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input logic [WIDTH-1:0] we1bit,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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input logic [DEPTH-1:0] wa1,
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input logic [WIDTH-1:0] wd1
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);
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logic [WIDTH-1:0] regs [2**DEPTH-1:0];
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integer i;
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@ -35,16 +35,16 @@
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`include "wally-config.vh"
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module sd_clk_fsm
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(
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input logic CLK,
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input logic i_RST,
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(* mark_debug = "true" *)output logic o_DONE,
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(* mark_debug = "true" *)input logic i_START,
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(* mark_debug = "true" *)input logic i_FATAL_ERROR,
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(* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz
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(* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init)
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(* mark_debug = "true" *)output logic o_G_CLK_SD_EN); // Turns gated clock (G_CLK_SD) off and on
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module sd_clk_fsm (
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input logic CLK,
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input logic i_RST,
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(* mark_debug = "true" *)output logic o_DONE,
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(* mark_debug = "true" *)input logic i_START,
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(* mark_debug = "true" *)input logic i_FATAL_ERROR,
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(* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz
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(* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init)
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(* mark_debug = "true" *)output logic o_G_CLK_SD_EN // Turns gated clock (G_CLK_SD) off and on
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);
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logic [3:0] w_next_state;
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@ -26,71 +26,66 @@
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`include "wally-config.vh"
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module sd_cmd_fsm
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(
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input logic CLK, // HS
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//i_SLOWER_CLK : in std_logic;
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input logic i_RST, // reset FSM,
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// MUST COME OUT OF RESET
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// SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
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output logic [18:0] o_TIMER_IN,
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input logic [18:0] i_TIMER_OUT,
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output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
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output logic [7:0] o_COUNTER_IN,
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input logic [7:0] i_COUNTER_OUT,
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output logic o_SD_CLK_EN, // Clock Gaters
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input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
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output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
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output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
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input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
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input logic [1:0] i_USES_DAT,
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input logic [6:0] i_OPCODE,
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input logic [2:0] i_R_TYPE,
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// bit masks
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input logic [31:0] i_NO_REDO_MASK,
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input logic [31:0] i_NO_REDO_ANS,
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input logic [31:0] i_NO_ERROR_MASK,
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input logic [31:0] i_NO_ERROR_ANS,
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(* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
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// TX Components
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output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
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output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
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output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
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output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
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// TX Memory
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output logic o_CMD_TX_IS_CMD55_RST,
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output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
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// 55, so the subsequent command is to be
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// viewed as ACMD by the SD card.
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// RX Components
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input logic i_SD_CMD_RX, // serial response input on SD_CMD
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output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
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input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
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input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
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output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
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input logic [6:0] i_RX_CRC7,
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// RX Memory
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output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
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// Communication to sd_dat_fsm
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output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
|
||||
input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
|
||||
(* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
|
||||
(* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
|
||||
// Commnuication to core
|
||||
output logic o_READY_FOR_READ, // tell core that I have completed initialization
|
||||
output logic o_SD_RESTARTING, // inform core the need to restart
|
||||
input logic i_READ_REQUEST, // core tells me to execute CMD17
|
||||
// Communication to Host
|
||||
output logic o_DAT_ERROR_FD_RST,
|
||||
output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
|
||||
output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
|
||||
|
||||
module sd_cmd_fsm (
|
||||
input logic CLK, // HS
|
||||
//i_SLOWER_CLK : in std_logic;
|
||||
input logic i_RST, // reset FSM,
|
||||
// MUST COME OUT OF RESET
|
||||
// SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
|
||||
output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
|
||||
output logic [18:0] o_TIMER_IN,
|
||||
input logic [18:0] i_TIMER_OUT,
|
||||
output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
|
||||
output logic [7:0] o_COUNTER_IN,
|
||||
input logic [7:0] i_COUNTER_OUT,
|
||||
output logic o_SD_CLK_EN, // Clock Gaters
|
||||
input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
|
||||
output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
|
||||
output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
|
||||
input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
|
||||
input logic [1:0] i_USES_DAT,
|
||||
input logic [6:0] i_OPCODE,
|
||||
input logic [2:0] i_R_TYPE,
|
||||
// bit masks
|
||||
input logic [31:0] i_NO_REDO_MASK,
|
||||
input logic [31:0] i_NO_REDO_ANS,
|
||||
input logic [31:0] i_NO_ERROR_MASK,
|
||||
input logic [31:0] i_NO_ERROR_ANS,
|
||||
(* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
|
||||
// TX Components
|
||||
output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
|
||||
output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
|
||||
output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
|
||||
output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
|
||||
// TX Memory
|
||||
output logic o_CMD_TX_IS_CMD55_RST,
|
||||
output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
|
||||
// 55, so the subsequent command is to be
|
||||
// viewed as ACMD by the SD card.
|
||||
// RX Components
|
||||
input logic i_SD_CMD_RX, // serial response input on SD_CMD
|
||||
output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
|
||||
input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
|
||||
input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
|
||||
output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
|
||||
input logic [6:0] i_RX_CRC7,
|
||||
// RX Memory
|
||||
output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
|
||||
// Communication to sd_dat_fsm
|
||||
output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
|
||||
input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
|
||||
(* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
|
||||
(* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
|
||||
// Commnuication to core
|
||||
output logic o_READY_FOR_READ, // tell core that I have completed initialization
|
||||
output logic o_SD_RESTARTING, // inform core the need to restart
|
||||
input logic i_READ_REQUEST, // core tells me to execute CMD17
|
||||
// Communication to Host
|
||||
output logic o_DAT_ERROR_FD_RST,
|
||||
output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
|
||||
output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
|
||||
logic [4:0] w_next_state;
|
||||
(* mark_debug = "true" *) logic [4:0] r_curr_state;
|
||||
|
@ -28,39 +28,38 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module sd_dat_fsm
|
||||
(
|
||||
input logic CLK, // HS Clock (48 MHz)
|
||||
input logic i_RST,
|
||||
// Timer module control
|
||||
input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
|
||||
output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
|
||||
output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
|
||||
input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
|
||||
// Nibble counter module control
|
||||
output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
|
||||
input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
|
||||
// CRC16 Generation control
|
||||
(* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
|
||||
(* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
|
||||
// For R1b
|
||||
output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
|
||||
(* mark_debug = "true" *)input logic i_DAT0_Q,
|
||||
// Storage Buffers for DAT bits read
|
||||
output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
|
||||
// From LUT
|
||||
(* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
|
||||
// For communicating with core
|
||||
output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
|
||||
output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
|
||||
// For communication with sd_cmd_fsm
|
||||
(* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
|
||||
(* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
|
||||
(* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
|
||||
(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST,
|
||||
(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
module sd_dat_fsm (
|
||||
input logic CLK, // HS Clock (48 MHz)
|
||||
input logic i_RST,
|
||||
// Timer module control
|
||||
input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
|
||||
output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
|
||||
output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
|
||||
input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
|
||||
// Nibble counter module control
|
||||
output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
|
||||
input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
|
||||
// CRC16 Generation control
|
||||
(* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
|
||||
(* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
|
||||
// For R1b
|
||||
output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
|
||||
(* mark_debug = "true" *)input logic i_DAT0_Q,
|
||||
// Storage Buffers for DAT bits read
|
||||
output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
|
||||
// From LUT
|
||||
(* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
|
||||
// For communicating with core
|
||||
output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
|
||||
output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
|
||||
// For communication with sd_cmd_fsm
|
||||
(* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
|
||||
(* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
|
||||
(* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
|
||||
(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST,
|
||||
(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
|
||||
(* mark_debug = "true" *) logic [3:0] r_curr_state;
|
||||
logic [3:0] w_next_state;
|
||||
|
@ -26,37 +26,36 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module sd_top #(parameter g_COUNT_WIDTH = 8)
|
||||
(
|
||||
input logic CLK, // 1.2 GHz (1.0 GHz typical)
|
||||
input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
|
||||
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
|
||||
// io_SD_CMD_z : inout std_logic; // SD CMD Bus
|
||||
(* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
|
||||
(* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
|
||||
(* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
|
||||
(* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
|
||||
(* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
|
||||
// For communication with core cpu
|
||||
input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
|
||||
output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
|
||||
// sd card is ready to read a 512 byte block to the core.
|
||||
// Held high during idle until i_READ_REQUEST is received
|
||||
output logic o_SD_RESTARTING, // inform core the need to restart
|
||||
module sd_top #(parameter g_COUNT_WIDTH = 8) (
|
||||
input logic CLK, // 1.2 GHz (1.0 GHz typical)
|
||||
input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
|
||||
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
|
||||
// io_SD_CMD_z : inout std_logic; // SD CMD Bus
|
||||
(* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
|
||||
(* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
|
||||
(* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
|
||||
(* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
|
||||
(* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
|
||||
// For communication with core cpu
|
||||
input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
|
||||
output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
|
||||
// sd card is ready to read a 512 byte block to the core.
|
||||
// Held high during idle until i_READ_REQUEST is received
|
||||
output logic o_SD_RESTARTING, // inform core the need to restart
|
||||
|
||||
input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will
|
||||
// pulse this bit high to indicate it wants the block at this address
|
||||
output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
|
||||
output logic [4095:0] ReadData, // full 512 bytes to Bus
|
||||
// being published
|
||||
output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid
|
||||
output logic o_LAST_NIBBLE, // pulse when last nibble is sent
|
||||
output logic [2:0] o_ERROR_CODE_Q, // indicates which error occured
|
||||
output logic o_FATAL_ERROR, // indicates that the FATAL ERROR register has updated
|
||||
// For tuning
|
||||
input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX,
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will
|
||||
// pulse this bit high to indicate it wants the block at this address
|
||||
output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
|
||||
output logic [4095:0] ReadData, // full 512 bytes to Bus
|
||||
// being published
|
||||
output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid
|
||||
output logic o_LAST_NIBBLE, // pulse when last nibble is sent
|
||||
output logic [2:0] o_ERROR_CODE_Q, // indicates which error occured
|
||||
output logic o_FATAL_ERROR, // indicates that the FATAL ERROR register has updated
|
||||
// For tuning
|
||||
input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX,
|
||||
input logic LIMIT_SD_TIMERS
|
||||
);
|
||||
|
||||
localparam logic c_CMD = 1'b0;
|
||||
localparam logic c_ACMD = 1'b1;
|
||||
|
@ -1,27 +1,26 @@
|
||||
|
||||
|
||||
module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
|
||||
(
|
||||
input clk_in1_p,
|
||||
input clk_in1_n,
|
||||
input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
|
||||
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
|
||||
// io_SD_CMD_z : inout std_logic; // SD CMD Bus
|
||||
inout SD_CMD, // CMD Response from card
|
||||
input [3:0] i_SD_DAT, // SD DAT Bus
|
||||
output o_SD_CLK, // SD CLK Bus
|
||||
// For communication with core cpu
|
||||
output o_READY_FOR_READ, // tells core that initialization sequence is completed and
|
||||
// sd card is ready to read a 512 byte block to the core.
|
||||
// Held high during idle until i_READ_REQUEST is received
|
||||
output o_SD_RESTARTING, // inform core the need to restart
|
||||
module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8) (
|
||||
input clk_in1_p,
|
||||
input clk_in1_n,
|
||||
input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
|
||||
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
|
||||
// io_SD_CMD_z : inout std_logic; // SD CMD Bus
|
||||
inout SD_CMD, // CMD Response from card
|
||||
input [3:0] i_SD_DAT, // SD DAT Bus
|
||||
output o_SD_CLK, // SD CLK Bus
|
||||
// For communication with core cpu
|
||||
output o_READY_FOR_READ, // tells core that initialization sequence is completed and
|
||||
// sd card is ready to read a 512 byte block to the core.
|
||||
// Held high during idle until i_READ_REQUEST is received
|
||||
output o_SD_RESTARTING, // inform core the need to restart
|
||||
|
||||
input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
|
||||
// pulse this bit high to indicate it wants the block at this address
|
||||
output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
|
||||
// being published
|
||||
output o_DATA_VALID // held high while data being read to core to indicate that it is valid
|
||||
);
|
||||
input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
|
||||
// pulse this bit high to indicate it wants the block at this address
|
||||
output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
|
||||
// being published
|
||||
output o_DATA_VALID // held high while data being read to core to indicate that it is valid
|
||||
);
|
||||
|
||||
wire CLK;
|
||||
wire LIMIT_SD_TIMERS;
|
||||
|
@ -26,13 +26,13 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module simple_timer #(parameter BUS_WIDTH = 4)
|
||||
(
|
||||
input logic [BUS_WIDTH-1:0] VALUE,
|
||||
input logic START,
|
||||
output logic FLAG,
|
||||
input logic RST,
|
||||
input logic CLK);
|
||||
module simple_timer #(parameter BUS_WIDTH = 4) (
|
||||
input logic [BUS_WIDTH-1:0] VALUE,
|
||||
input logic START,
|
||||
output logic FLAG,
|
||||
input logic RST,
|
||||
input logic CLK
|
||||
);
|
||||
|
||||
|
||||
logic [BUS_WIDTH-1:0] count;
|
||||
|
@ -29,13 +29,13 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module sipo_generic_ce #(g_BUS_WIDTH)
|
||||
(input logic clk,
|
||||
input logic rst,
|
||||
input logic i_enable, // data valid, write to register
|
||||
input logic i_message_bit, // serial data
|
||||
output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data
|
||||
);
|
||||
module sipo_generic_ce #(g_BUS_WIDTH) (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic i_enable, // data valid, write to register
|
||||
input logic i_message_bit, // serial data
|
||||
output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data
|
||||
);
|
||||
|
||||
logic [g_BUS_WIDTH-1:0] w_reg_d;
|
||||
logic [g_BUS_WIDTH-1:0] r_reg_q;
|
||||
|
@ -26,15 +26,15 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module up_down_counter #(parameter integer WIDTH=32)
|
||||
(
|
||||
input logic [WIDTH-1:0] CountIn,
|
||||
output logic [WIDTH-1:0] CountOut,
|
||||
input logic Load,
|
||||
input logic Enable,
|
||||
input logic UpDown,
|
||||
input logic clk,
|
||||
input logic reset);
|
||||
module up_down_counter #(parameter integer WIDTH=32) (
|
||||
input logic [WIDTH-1:0] CountIn,
|
||||
output logic [WIDTH-1:0] CountOut,
|
||||
input logic Load,
|
||||
input logic Enable,
|
||||
input logic UpDown,
|
||||
input logic clk,
|
||||
input logic reset
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] NextCount;
|
||||
logic [WIDTH-1:0] CountP1;
|
||||
|
@ -13,6 +13,8 @@
|
||||
// Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
|
||||
// Timeout not ye implemented***
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 15
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
|
@ -8,6 +8,8 @@
|
||||
// Emulates interface of Texas Instruments PC165550D
|
||||
// Compatible with UART in Imperas Virtio model ***
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 15
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
|
@ -7,6 +7,8 @@
|
||||
// Purpose: System-on-Chip components outside the core
|
||||
// Memories, peripherals, external bus control
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
|
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//
|
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// A component of the CORE-V-WALLY configurable RISC-V project.
|
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//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
|
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Reference in New Issue
Block a user