From 41c7d5c510b52f6f2f1a781cd2503642d63234fd Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 14 Jan 2023 06:15:35 -0800
Subject: [PATCH] uncore cleanup
---
pipelined/src/uncore/ahbapbbridge.sv | 2 +
pipelined/src/uncore/clint_apb.sv | 2 +
pipelined/src/uncore/gpio_apb.sv | 2 +
pipelined/src/uncore/plic_apb.sv | 2 +
pipelined/src/uncore/ram_ahb.sv | 2 +
pipelined/src/uncore/rom_ahb.sv | 2 +
pipelined/src/uncore/sdc/SDC.sv | 62 ++++-----
pipelined/src/uncore/sdc/SDCcounter.sv | 16 +--
pipelined/src/uncore/sdc/clkdivider.sv | 5 +-
pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 13 +-
pipelined/src/uncore/sdc/crc7_pipo.sv | 13 +-
pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 14 +-
pipelined/src/uncore/sdc/piso_generic_ce.sv | 17 ++-
pipelined/src/uncore/sdc/proposed-sdc.txt | 55 --------
.../src/uncore/sdc/regfile_p2r1w1_nibo.sv | 17 +--
.../src/uncore/sdc/regfile_p2r1w1bwen.sv | 17 +--
pipelined/src/uncore/sdc/sd_clk_fsm.sv | 20 +--
pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 125 +++++++++---------
pipelined/src/uncore/sdc/sd_dat_fsm.sv | 65 +++++----
pipelined/src/uncore/sdc/sd_top.sv | 61 +++++----
pipelined/src/uncore/sdc/sd_top_wrapper.v | 43 +++---
pipelined/src/uncore/sdc/simple_timer.sv | 14 +-
pipelined/src/uncore/sdc/sipo_generic_ce.sv | 14 +-
pipelined/src/uncore/sdc/up_down_counter.sv | 18 +--
pipelined/src/uncore/uartPC16550D.sv | 2 +
pipelined/src/uncore/uart_apb.sv | 2 +
pipelined/src/uncore/uncore.sv | 2 +
27 files changed, 282 insertions(+), 325 deletions(-)
delete mode 100644 pipelined/src/uncore/sdc/proposed-sdc.txt
diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv
index 9c72d1f52..44a2335fd 100644
--- a/pipelined/src/uncore/ahbapbbridge.sv
+++ b/pipelined/src/uncore/ahbapbbridge.sv
@@ -5,6 +5,8 @@
//
// Purpose: AHB to APB bridge
//
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv
index 679d2c8e8..ba9ecc7cc 100644
--- a/pipelined/src/uncore/clint_apb.sv
+++ b/pipelined/src/uncore/clint_apb.sv
@@ -7,6 +7,8 @@
// Purpose: Core-Local Interruptor
// See FE310-G002-Manual-v19p05 for specifications
//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv
index 1cc33f07f..475d5c85e 100644
--- a/pipelined/src/uncore/gpio_apb.sv
+++ b/pipelined/src/uncore/gpio_apb.sv
@@ -8,6 +8,8 @@
// See FE310-G002-Manual-v19p05 for specifications
// No interrupts, drive strength, or pull-ups supported
//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv
index c39c0329e..6c90e65ea 100644
--- a/pipelined/src/uncore/plic_apb.sv
+++ b/pipelined/src/uncore/plic_apb.sv
@@ -9,6 +9,8 @@
// With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
// Supports only 1 target core and only a global threshold.
//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
// *** Big questions:
// Do we detect requests as level-triggered or edge-trigged?
// If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests?
diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv
index 1834f21b9..14c8a8a7c 100644
--- a/pipelined/src/uncore/ram_ahb.sv
+++ b/pipelined/src/uncore/ram_ahb.sv
@@ -6,6 +6,8 @@
//
// Purpose: On-chip RAM, external to core, with AHB interface
//
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv
index 72bfbe715..b009185ba 100644
--- a/pipelined/src/uncore/rom_ahb.sv
+++ b/pipelined/src/uncore/rom_ahb.sv
@@ -6,6 +6,8 @@
//
// Purpose: On-chip ROM, external to core
//
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv
index b8c5cfdee..f8cb97743 100644
--- a/pipelined/src/uncore/sdc/SDC.sv
+++ b/pipelined/src/uncore/sdc/SDC.sv
@@ -28,44 +28,44 @@
`define SDCCLKDIV -8'd3
-module SDC
- (input logic HCLK,
- input logic HRESETn,
- input logic HSELSDC,
- input logic [4:0] HADDR,
- input logic HWRITE,
- input logic HREADY,
- input logic [1:0] HTRANS,
- input logic [`XLEN-1:0] HWDATA,
- output logic [`XLEN-1:0] HREADSDC,
- output logic HRESPSDC,
- output logic HREADYSDC,
+module SDC (
+ input logic HCLK,
+ input logic HRESETn,
+ input logic HSELSDC,
+ input logic [4:0] HADDR,
+ input logic HWRITE,
+ input logic HREADY,
+ input logic [1:0] HTRANS,
+ input logic [`XLEN-1:0] HWDATA,
+ output logic [`XLEN-1:0] HREADSDC,
+ output logic HRESPSDC,
+ output logic HREADYSDC,
- //sd card interface
- // place the tristate drivers at the top. this level
- // will use dedicated 1 direction ports.
- output logic SDCCmdOut,
- input logic SDCCmdIn,
- output logic SDCCmdOE,
- input logic [3:0] SDCDatIn,
- output logic SDCCLK,
+ //sd card interface
+ // place the tristate drivers at the top. this level
+ // will use dedicated 1 direction ports.
+ output logic SDCCmdOut,
+ input logic SDCCmdIn,
+ output logic SDCCmdOE,
+ input logic [3:0] SDCDatIn,
+ output logic SDCCLK,
+ // interrupt to PLIC
+ output logic SDCIntM
+);
- // interrupt to PLIC
- output logic SDCIntM);
-
- logic InitTrans;
- logic RegRead;
- logic RegWrite;
- logic [4:0] HADDRDelay;
+ logic InitTrans;
+ logic RegRead;
+ logic RegWrite;
+ logic [4:0] HADDRDelay;
// Register outputs
- logic signed [7:0] CLKDiv;
- logic [2:0] Command;
- logic [63:9] Address;
+ logic signed [7:0] CLKDiv;
+ logic [2:0] Command;
+ logic [63:9] Address;
- logic SDCDone;
+ logic SDCDone;
logic [2:0] ErrorCode;
logic InvalidCommand;
diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv
index e6107c041..cac17b7cd 100644
--- a/pipelined/src/uncore/sdc/SDCcounter.sv
+++ b/pipelined/src/uncore/sdc/SDCcounter.sv
@@ -27,14 +27,14 @@
`include "wally-config.vh"
-module SDCcounter #(parameter integer WIDTH=32)
- (
- input logic [WIDTH-1:0] CountIn,
- output logic [WIDTH-1:0] CountOut,
- input logic Load,
- input logic Enable,
- input logic clk,
- input logic reset);
+module SDCcounter #(parameter integer WIDTH=32) (
+ input logic [WIDTH-1:0] CountIn,
+ output logic [WIDTH-1:0] CountOut,
+ input logic Load,
+ input logic Enable,
+ input logic clk,
+ input logic reset
+);
logic [WIDTH-1:0] NextCount;
diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv
index d475b395f..a877b35f3 100644
--- a/pipelined/src/uncore/sdc/clkdivider.sv
+++ b/pipelined/src/uncore/sdc/clkdivider.sv
@@ -27,8 +27,7 @@
`include "wally-config.vh"
-module clkdivider #(parameter integer g_COUNT_WIDTH)
- (
+module clkdivider #(parameter integer g_COUNT_WIDTH) (
input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX, //((Divide by value)/2) - 1
input logic i_EN, //Enable frequency division of i_clk
input logic i_CLK, // 1.2 GHz Base clock
@@ -36,7 +35,7 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
// i_RST must NOT be a_RST, it needs to be synchronized with the 50 MHz Clock to load the
// counter's initial value
output logic o_CLK // frequency divided clock
- );
+);
logic [g_COUNT_WIDTH-1:0] r_count_out; // wider for sign
diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv
index 6baabdba1..e229466b1 100644
--- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv
+++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv
@@ -28,12 +28,13 @@
`include "wally-config.vh"
-module crc16_sipo_np_ce
- (input logic CLK, // sequential device
- input logic RST, // initial calue of CRC register must be "0000_0000_0000_0000"
- input logic i_enable, // input is valid
- input logic i_message_bit,
- output logic [15:0] o_crc16);
+module crc16_sipo_np_ce(
+ input logic CLK, // sequential device
+ input logic RST, // initial calue of CRC register must be "0000_0000_0000_0000"
+ input logic i_enable, // input is valid
+ input logic i_message_bit,
+ output logic [15:0] o_crc16
+);
logic [15:0] w_crc16_d;
diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv
index a2dc06fc4..213b2e029 100644
--- a/pipelined/src/uncore/sdc/crc7_pipo.sv
+++ b/pipelined/src/uncore/sdc/crc7_pipo.sv
@@ -29,12 +29,13 @@
`include "wally-config.vh"
-module crc7_pipo
- (input logic [39:0] i_DATA,
- input logic i_CRC_ENABLE,
- input logic RST,
- input logic CLK,
- output logic [6:0] o_CRC);
+module crc7_pipo (
+ input logic [39:0] i_DATA,
+ input logic i_CRC_ENABLE,
+ input logic RST,
+ input logic CLK,
+ output logic [6:0] o_CRC
+);
logic [6:0] r_lfsr_q;
logic [6:0] w_lfsr_d;
diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv
index 3a52b5c41..4eddfa7e8 100644
--- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv
+++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv
@@ -27,13 +27,13 @@
`include "wally-config.vh"
-module crc7_sipo_np_ce
- (
- input logic clk,
- input logic rst,// initial CRC value must be b"000_0000"
- input logic i_enable,
- input logic i_message_bit,
- output logic [6:0] o_crc7);
+module crc7_sipo_np_ce(
+ input logic clk,
+ input logic rst,// initial CRC value must be b"000_0000"
+ input logic i_enable,
+ input logic i_message_bit,
+ output logic [6:0] o_crc7
+);
logic [6:0] w_crc7_d;
diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv
index f134212c5..fb7f70949 100644
--- a/pipelined/src/uncore/sdc/piso_generic_ce.sv
+++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv
@@ -25,17 +25,16 @@
`include "wally-config.vh"
-module piso_generic_ce #(parameter integer g_BUS_WIDTH)
- (
- input logic clk,
- input logic i_load,
- input logic [g_BUS_WIDTH-1:0] i_data,
- input logic i_en,
- output o_data);
+module piso_generic_ce #(parameter integer g_BUS_WIDTH) (
+ input logic clk,
+ input logic i_load,
+ input logic [g_BUS_WIDTH-1:0] i_data,
+ input logic i_en,
+ output o_data);
- logic [g_BUS_WIDTH-1:0] w_reg_d;
- logic [g_BUS_WIDTH-1:0] r_reg_q;
+ logic [g_BUS_WIDTH-1:0] w_reg_d;
+ logic [g_BUS_WIDTH-1:0] r_reg_q;
flopenr #(g_BUS_WIDTH)
shiftReg(.clk(clk),
diff --git a/pipelined/src/uncore/sdc/proposed-sdc.txt b/pipelined/src/uncore/sdc/proposed-sdc.txt
deleted file mode 100644
index 893143dd0..000000000
--- a/pipelined/src/uncore/sdc/proposed-sdc.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-SD Flash interface
-
-regsiter map:
-1. clock divider
-2. address
-3. data register
-4. command register
-5. size register
- Number of bytes to read or write.
-6. status register
- 1. bits 11 to 0: bytes currently in the buffer
- 2. bits 12 to 29: reservered
- 3. bit 30: fault
- 4. bit 31: busy
- 5. bits XLEN-1 to 32: reservered
-
-
-
-non dma read operation
-1. write the address regsiter
-2. write the command register to read
-3. wait for interrupt or pool on status
-4. Check status for fault and number of bytes.
-5. read the data register for 512 bytes. (64 ld, or 128 lw)
-
-
-non dma write operation
-1. write address register
-2. write data register for 512 bytes. (64 sd, or 128 sw)
-3. write command register to write data to flash
-4. wait for interrupt or pool on status
-5. check status for fault and number of bytes written.
-
-implement dma transfers later
-
-
-interrupts
-1. operation done
-2. bus error (more of an exception)
- Occurs if attempting to do an operation while the flash controller is busy.
- ie. if status[31] is set generate an interrupt
- This is tricky in a multiprocessor environment.
-
-
-
-
-tasks
-1. [-] Remove all AFRL identifiers
-2. [X] get the existing sdc compiled on wally.
- 1. [X] use wally primatives over tcore's
-3. build abhlite interface with the above registers and necessary fsm.
- 1. [ ] The sd card reader uses a 4 bit data interface. We can change this to be something
- more pratical.
-4. write test programs
-5. [X] Convert VHDL to system verilog
diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv
index e63188377..52e78426b 100644
--- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv
+++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv
@@ -25,14 +25,15 @@
`include "wally-config.vh"
-module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
- (input logic clk,
- input logic we1,
- input logic [DEPTH-1:0] ra1,
- output logic [WIDTH-1:0] rd1,
- output logic [(2**DEPTH)*WIDTH-1:0] Rd1All,
- input logic [DEPTH-1:0] wa1,
- input logic [WIDTH-1:0] wd1);
+module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4) (
+ input logic clk,
+ input logic we1,
+ input logic [DEPTH-1:0] ra1,
+ output logic [WIDTH-1:0] rd1,
+ output logic [(2**DEPTH)*WIDTH-1:0] Rd1All,
+ input logic [DEPTH-1:0] wa1,
+ input logic [WIDTH-1:0] wd1
+);
logic [WIDTH-1:0] regs [2**DEPTH-1:0];
genvar index;
diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv
index bd050c4e5..bfa7c7148 100644
--- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv
+++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv
@@ -25,14 +25,15 @@
`include "wally-config.vh"
-module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
- (input logic clk,
- input logic we1,
- input logic [WIDTH-1:0] we1bit,
- input logic [DEPTH-1:0] ra1,
- output logic [WIDTH-1:0] rd1,
- input logic [DEPTH-1:0] wa1,
- input logic [WIDTH-1:0] wd1);
+module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)(
+ input logic clk,
+ input logic we1,
+ input logic [WIDTH-1:0] we1bit,
+ input logic [DEPTH-1:0] ra1,
+ output logic [WIDTH-1:0] rd1,
+ input logic [DEPTH-1:0] wa1,
+ input logic [WIDTH-1:0] wd1
+);
logic [WIDTH-1:0] regs [2**DEPTH-1:0];
integer i;
diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv
index 6ec8ada13..949b0dc12 100644
--- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv
+++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv
@@ -35,16 +35,16 @@
`include "wally-config.vh"
-module sd_clk_fsm
- (
- input logic CLK,
- input logic i_RST,
- (* mark_debug = "true" *)output logic o_DONE,
- (* mark_debug = "true" *)input logic i_START,
- (* mark_debug = "true" *)input logic i_FATAL_ERROR,
- (* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz
- (* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init)
- (* mark_debug = "true" *)output logic o_G_CLK_SD_EN); // Turns gated clock (G_CLK_SD) off and on
+module sd_clk_fsm (
+ input logic CLK,
+ input logic i_RST,
+ (* mark_debug = "true" *)output logic o_DONE,
+ (* mark_debug = "true" *)input logic i_START,
+ (* mark_debug = "true" *)input logic i_FATAL_ERROR,
+ (* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz
+ (* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init)
+ (* mark_debug = "true" *)output logic o_G_CLK_SD_EN // Turns gated clock (G_CLK_SD) off and on
+);
logic [3:0] w_next_state;
diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv
index 4769e6eaa..a5512031e 100644
--- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv
+++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv
@@ -26,71 +26,66 @@
`include "wally-config.vh"
-module sd_cmd_fsm
- (
-
- input logic CLK, // HS
- //i_SLOWER_CLK : in std_logic;
- input logic i_RST, // reset FSM,
- // MUST COME OUT OF RESET
- // SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
- output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
- output logic [18:0] o_TIMER_IN,
- input logic [18:0] i_TIMER_OUT,
- output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
- output logic [7:0] o_COUNTER_IN,
- input logic [7:0] i_COUNTER_OUT,
- output logic o_SD_CLK_EN, // Clock Gaters
- input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
- output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
- output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
- input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
- input logic [1:0] i_USES_DAT,
- input logic [6:0] i_OPCODE,
- input logic [2:0] i_R_TYPE,
- // bit masks
- input logic [31:0] i_NO_REDO_MASK,
- input logic [31:0] i_NO_REDO_ANS,
- input logic [31:0] i_NO_ERROR_MASK,
- input logic [31:0] i_NO_ERROR_ANS,
- (* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
- // TX Components
- output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
- output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
- output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
- output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
- // TX Memory
- output logic o_CMD_TX_IS_CMD55_RST,
- output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
- // 55, so the subsequent command is to be
- // viewed as ACMD by the SD card.
- // RX Components
- input logic i_SD_CMD_RX, // serial response input on SD_CMD
- output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
-
- input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
- input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
- output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
- input logic [6:0] i_RX_CRC7,
- // RX Memory
- output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
- // Communication to sd_dat_fsm
- output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
- input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
- (* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
- (* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
- // Commnuication to core
- output logic o_READY_FOR_READ, // tell core that I have completed initialization
- output logic o_SD_RESTARTING, // inform core the need to restart
- input logic i_READ_REQUEST, // core tells me to execute CMD17
- // Communication to Host
- output logic o_DAT_ERROR_FD_RST,
- output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
- output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
- input logic LIMIT_SD_TIMERS
- );
-
-
+module sd_cmd_fsm (
+ input logic CLK, // HS
+ //i_SLOWER_CLK : in std_logic;
+ input logic i_RST, // reset FSM,
+ // MUST COME OUT OF RESET
+ // SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
+ output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
+ output logic [18:0] o_TIMER_IN,
+ input logic [18:0] i_TIMER_OUT,
+ output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
+ output logic [7:0] o_COUNTER_IN,
+ input logic [7:0] i_COUNTER_OUT,
+ output logic o_SD_CLK_EN, // Clock Gaters
+ input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
+ output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
+ output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
+ input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
+ input logic [1:0] i_USES_DAT,
+ input logic [6:0] i_OPCODE,
+ input logic [2:0] i_R_TYPE,
+ // bit masks
+ input logic [31:0] i_NO_REDO_MASK,
+ input logic [31:0] i_NO_REDO_ANS,
+ input logic [31:0] i_NO_ERROR_MASK,
+ input logic [31:0] i_NO_ERROR_ANS,
+ (* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
+ // TX Components
+ output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
+ output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
+ output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
+ output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
+ // TX Memory
+ output logic o_CMD_TX_IS_CMD55_RST,
+ output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
+ // 55, so the subsequent command is to be
+ // viewed as ACMD by the SD card.
+ // RX Components
+ input logic i_SD_CMD_RX, // serial response input on SD_CMD
+ output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
+ input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
+ input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
+ output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
+ input logic [6:0] i_RX_CRC7,
+ // RX Memory
+ output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
+ // Communication to sd_dat_fsm
+ output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
+ input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
+ (* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
+ (* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
+ // Commnuication to core
+ output logic o_READY_FOR_READ, // tell core that I have completed initialization
+ output logic o_SD_RESTARTING, // inform core the need to restart
+ input logic i_READ_REQUEST, // core tells me to execute CMD17
+ // Communication to Host
+ output logic o_DAT_ERROR_FD_RST,
+ output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
+ output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
+ input logic LIMIT_SD_TIMERS
+);
logic [4:0] w_next_state;
(* mark_debug = "true" *) logic [4:0] r_curr_state;
diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv
index 476687523..24c2c2bc2 100644
--- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv
+++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv
@@ -28,39 +28,38 @@
`include "wally-config.vh"
-module sd_dat_fsm
- (
- input logic CLK, // HS Clock (48 MHz)
- input logic i_RST,
- // Timer module control
- input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
- output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
- output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
- input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
- // Nibble counter module control
- output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
- input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
- // CRC16 Generation control
- (* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
- (* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
- // For R1b
- output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
- (* mark_debug = "true" *)input logic i_DAT0_Q,
- // Storage Buffers for DAT bits read
- output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
- // From LUT
- (* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
- // For communicating with core
- output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
- output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
- // For communication with sd_cmd_fsm
- (* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
- (* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
- (* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
- (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST,
- (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
- input logic LIMIT_SD_TIMERS
- );
+module sd_dat_fsm (
+ input logic CLK, // HS Clock (48 MHz)
+ input logic i_RST,
+ // Timer module control
+ input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
+ output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
+ output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
+ input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
+ // Nibble counter module control
+ output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
+ input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
+ // CRC16 Generation control
+ (* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
+ (* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
+ // For R1b
+ output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
+ (* mark_debug = "true" *)input logic i_DAT0_Q,
+ // Storage Buffers for DAT bits read
+ output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
+ // From LUT
+ (* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
+ // For communicating with core
+ output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
+ output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
+ // For communication with sd_cmd_fsm
+ (* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
+ (* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
+ (* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
+ (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST,
+ (* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
+ input logic LIMIT_SD_TIMERS
+);
(* mark_debug = "true" *) logic [3:0] r_curr_state;
logic [3:0] w_next_state;
diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv
index 90ae706ae..2344d2876 100644
--- a/pipelined/src/uncore/sdc/sd_top.sv
+++ b/pipelined/src/uncore/sdc/sd_top.sv
@@ -26,37 +26,36 @@
`include "wally-config.vh"
-module sd_top #(parameter g_COUNT_WIDTH = 8)
- (
- input logic CLK, // 1.2 GHz (1.0 GHz typical)
- input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
- // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
- // io_SD_CMD_z : inout std_logic; // SD CMD Bus
- (* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
- (* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
- (* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
- (* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
- (* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
- // For communication with core cpu
- input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
- output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
- // sd card is ready to read a 512 byte block to the core.
- // Held high during idle until i_READ_REQUEST is received
- output logic o_SD_RESTARTING, // inform core the need to restart
-
- input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will
- // pulse this bit high to indicate it wants the block at this address
- output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
- output logic [4095:0] ReadData, // full 512 bytes to Bus
- // being published
- output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid
- output logic o_LAST_NIBBLE, // pulse when last nibble is sent
- output logic [2:0] o_ERROR_CODE_Q, // indicates which error occured
- output logic o_FATAL_ERROR, // indicates that the FATAL ERROR register has updated
- // For tuning
- input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX,
- input logic LIMIT_SD_TIMERS
- );
+module sd_top #(parameter g_COUNT_WIDTH = 8) (
+ input logic CLK, // 1.2 GHz (1.0 GHz typical)
+ input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
+ // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
+ // io_SD_CMD_z : inout std_logic; // SD CMD Bus
+ (* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
+ (* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
+ (* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
+ (* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
+ (* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
+ // For communication with core cpu
+ input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
+ output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
+ // sd card is ready to read a 512 byte block to the core.
+ // Held high during idle until i_READ_REQUEST is received
+ output logic o_SD_RESTARTING, // inform core the need to restart
+
+ input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will
+ // pulse this bit high to indicate it wants the block at this address
+ output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
+ output logic [4095:0] ReadData, // full 512 bytes to Bus
+ // being published
+ output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid
+ output logic o_LAST_NIBBLE, // pulse when last nibble is sent
+ output logic [2:0] o_ERROR_CODE_Q, // indicates which error occured
+ output logic o_FATAL_ERROR, // indicates that the FATAL ERROR register has updated
+ // For tuning
+ input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX,
+ input logic LIMIT_SD_TIMERS
+);
localparam logic c_CMD = 1'b0;
localparam logic c_ACMD = 1'b1;
diff --git a/pipelined/src/uncore/sdc/sd_top_wrapper.v b/pipelined/src/uncore/sdc/sd_top_wrapper.v
index e2230d608..32fedfaa8 100644
--- a/pipelined/src/uncore/sdc/sd_top_wrapper.v
+++ b/pipelined/src/uncore/sdc/sd_top_wrapper.v
@@ -1,27 +1,26 @@
-module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
- (
- input clk_in1_p,
- input clk_in1_n,
- input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
- // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
- // io_SD_CMD_z : inout std_logic; // SD CMD Bus
- inout SD_CMD, // CMD Response from card
- input [3:0] i_SD_DAT, // SD DAT Bus
- output o_SD_CLK, // SD CLK Bus
- // For communication with core cpu
- output o_READY_FOR_READ, // tells core that initialization sequence is completed and
- // sd card is ready to read a 512 byte block to the core.
- // Held high during idle until i_READ_REQUEST is received
- output o_SD_RESTARTING, // inform core the need to restart
-
- input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
- // pulse this bit high to indicate it wants the block at this address
- output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
- // being published
- output o_DATA_VALID // held high while data being read to core to indicate that it is valid
- );
+module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8) (
+ input clk_in1_p,
+ input clk_in1_n,
+ input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
+ // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
+ // io_SD_CMD_z : inout std_logic; // SD CMD Bus
+ inout SD_CMD, // CMD Response from card
+ input [3:0] i_SD_DAT, // SD DAT Bus
+ output o_SD_CLK, // SD CLK Bus
+ // For communication with core cpu
+ output o_READY_FOR_READ, // tells core that initialization sequence is completed and
+ // sd card is ready to read a 512 byte block to the core.
+ // Held high during idle until i_READ_REQUEST is received
+ output o_SD_RESTARTING, // inform core the need to restart
+
+ input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
+ // pulse this bit high to indicate it wants the block at this address
+ output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
+ // being published
+ output o_DATA_VALID // held high while data being read to core to indicate that it is valid
+);
wire CLK;
wire LIMIT_SD_TIMERS;
diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv
index ad04877e0..6c6014d3e 100644
--- a/pipelined/src/uncore/sdc/simple_timer.sv
+++ b/pipelined/src/uncore/sdc/simple_timer.sv
@@ -26,13 +26,13 @@
`include "wally-config.vh"
-module simple_timer #(parameter BUS_WIDTH = 4)
- (
- input logic [BUS_WIDTH-1:0] VALUE,
- input logic START,
- output logic FLAG,
- input logic RST,
- input logic CLK);
+module simple_timer #(parameter BUS_WIDTH = 4) (
+ input logic [BUS_WIDTH-1:0] VALUE,
+ input logic START,
+ output logic FLAG,
+ input logic RST,
+ input logic CLK
+);
logic [BUS_WIDTH-1:0] count;
diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv
index 54f513c31..39d61d588 100644
--- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv
+++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv
@@ -29,13 +29,13 @@
`include "wally-config.vh"
-module sipo_generic_ce #(g_BUS_WIDTH)
- (input logic clk,
- input logic rst,
- input logic i_enable, // data valid, write to register
- input logic i_message_bit, // serial data
- output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data
- );
+module sipo_generic_ce #(g_BUS_WIDTH) (
+ input logic clk,
+ input logic rst,
+ input logic i_enable, // data valid, write to register
+ input logic i_message_bit, // serial data
+ output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data
+);
logic [g_BUS_WIDTH-1:0] w_reg_d;
logic [g_BUS_WIDTH-1:0] r_reg_q;
diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv
index 685f74084..db8502e46 100644
--- a/pipelined/src/uncore/sdc/up_down_counter.sv
+++ b/pipelined/src/uncore/sdc/up_down_counter.sv
@@ -26,15 +26,15 @@
`include "wally-config.vh"
-module up_down_counter #(parameter integer WIDTH=32)
- (
- input logic [WIDTH-1:0] CountIn,
- output logic [WIDTH-1:0] CountOut,
- input logic Load,
- input logic Enable,
- input logic UpDown,
- input logic clk,
- input logic reset);
+module up_down_counter #(parameter integer WIDTH=32) (
+ input logic [WIDTH-1:0] CountIn,
+ output logic [WIDTH-1:0] CountOut,
+ input logic Load,
+ input logic Enable,
+ input logic UpDown,
+ input logic clk,
+ input logic reset
+);
logic [WIDTH-1:0] NextCount;
logic [WIDTH-1:0] CountP1;
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index 3217c3c67..39f403330 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -13,6 +13,8 @@
// Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
// Timeout not ye implemented***
//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv
index d5389bb32..b7d2b0d50 100644
--- a/pipelined/src/uncore/uart_apb.sv
+++ b/pipelined/src/uncore/uart_apb.sv
@@ -8,6 +8,8 @@
// Emulates interface of Texas Instruments PC165550D
// Compatible with UART in Imperas Virtio model ***
//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv
index 7a6c3dc08..630b89337 100644
--- a/pipelined/src/uncore/uncore.sv
+++ b/pipelined/src/uncore/uncore.sv
@@ -7,6 +7,8 @@
// Purpose: System-on-Chip components outside the core
// Memories, peripherals, external bus control
//
+// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
+//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University