uncore cleanup

pipelined/src/uncore/ahbapbbridge.sv

@@ -5,6 +5,8 @@
 //
 // Purpose: AHB to APB bridge
 // 
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/clint_apb.sv

@@ -7,6 +7,8 @@
 // Purpose: Core-Local Interruptor
 //   See FE310-G002-Manual-v19p05 for specifications
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/gpio_apb.sv

@@ -8,6 +8,8 @@
 //   See FE310-G002-Manual-v19p05 for specifications
 //   No interrupts, drive strength, or pull-ups supported
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/plic_apb.sv

@@ -9,6 +9,8 @@
 //   With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
 //   Supports only 1 target core and only a global threshold.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
 // *** Big questions:
 //  Do we detect requests as level-triggered or edge-trigged?
 //  If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests?

pipelined/src/uncore/ram_ahb.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: On-chip RAM, external to core, with AHB interface
 // 
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/rom_ahb.sv

@@ -6,6 +6,8 @@
 //
 // Purpose: On-chip ROM, external to core
 // 
+// Documentation: RISC-V System on Chip Design Chapter 6
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/sdc/SDC.sv

@@ -28,8 +28,8 @@
 
 `define SDCCLKDIV -8'd3
 
-module SDC 
-  (input  logic             HCLK, 
+module SDC (
+  input  logic             HCLK, 
   input  logic 		         HRESETn,
   input  logic 		         HSELSDC,
   input  logic [4:0] 	     HADDR,
@@ -49,9 +49,9 @@ module SDC
   output logic 	           SDCCmdOE,
   input  logic [3:0] 	     SDCDatIn,
   output logic 	           SDCCLK,
-
   // interrupt to PLIC
-   output logic 	    SDCIntM);
+  output logic 	           SDCIntM
+);
 
   logic 		               InitTrans;
   logic 		               RegRead;

pipelined/src/uncore/sdc/SDCcounter.sv

@@ -27,14 +27,14 @@
 
 `include "wally-config.vh"
 
-module SDCcounter #(parameter integer WIDTH=32)
-  (
+module SDCcounter #(parameter integer WIDTH=32) (
   input  logic [WIDTH-1:0]   CountIn,
   output logic [WIDTH-1:0]   CountOut,
   input  logic 		          Load,
   input  logic 		          Enable,
   input  logic 		          clk,
-   input logic 		    reset);
+  input  logic 		          reset
+);
 
   logic [WIDTH-1:0] NextCount;
  

pipelined/src/uncore/sdc/clkdivider.sv

@@ -27,8 +27,7 @@
 
 `include "wally-config.vh"
 
-module clkdivider #(parameter integer g_COUNT_WIDTH)
-  (
+module clkdivider #(parameter integer g_COUNT_WIDTH) (
    input logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX, //((Divide by value)/2) - 1
    input logic 			   i_EN, //Enable frequency division of i_clk
    input logic 			   i_CLK, // 1.2 GHz Base clock

pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv

@@ -28,12 +28,13 @@
 
 `include "wally-config.vh"
 
-module crc16_sipo_np_ce
-  (input logic CLK, // sequential device
+module crc16_sipo_np_ce(
+  input  logic         CLK, // sequential device
   input  logic 	       RST, // initial calue of CRC register must be "0000_0000_0000_0000"
   input  logic 	       i_enable, // input is valid
   input  logic 	       i_message_bit,
-   output logic [15:0] o_crc16);
+  output logic [15:0]  o_crc16
+);
 
   logic [15:0] 	       w_crc16_d;
 

pipelined/src/uncore/sdc/crc7_pipo.sv

@@ -29,12 +29,13 @@
 
 `include "wally-config.vh"
 
-module crc7_pipo
-  (input logic [39:0] i_DATA,
+module crc7_pipo (
+  input logic [39:0] i_DATA,
   input logic 	      i_CRC_ENABLE,
   input logic 	      RST,
   input logic 	      CLK,
-   output logic [6:0] o_CRC);
+  output logic [6:0] o_CRC
+);
   
   logic [6:0] 	      r_lfsr_q;
   logic [6:0] 	      w_lfsr_d;

pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv

@@ -27,13 +27,13 @@
 
 `include "wally-config.vh"
 
-module crc7_sipo_np_ce
-  (
+module crc7_sipo_np_ce(
   input  logic 	      clk,
   input  logic 	      rst,//      initial CRC value must be b"000_0000"
   input  logic 	      i_enable,
   input  logic 	      i_message_bit,
-   output logic [6:0] o_crc7);
+  output logic [6:0] o_crc7
+);
 
 
   logic [6:0] 	      w_crc7_d;

pipelined/src/uncore/sdc/piso_generic_ce.sv

@@ -25,8 +25,7 @@
 
 `include "wally-config.vh"
 
-module piso_generic_ce #(parameter integer g_BUS_WIDTH)
-  (
+module piso_generic_ce #(parameter integer g_BUS_WIDTH) (
    input  logic 			            clk, 
    input  logic 			            i_load, 
    input  logic [g_BUS_WIDTH-1:0] i_data, 

pipelined/src/uncore/sdc/proposed-sdc.txt

@@ -1,55 +0,0 @@
-SD Flash interface
-
-regsiter map:
-1. clock divider
-2. address
-3. data register
-4. command register
-5. size register
-   Number of bytes to read or write.
-6. status register
-   1. bits 11 to 0: bytes currently in the buffer
-   2. bits 12 to 29: reservered
-   3. bit 30: fault
-   4. bit 31: busy
-   5. bits XLEN-1 to 32: reservered
-
-
-
-non dma read operation
-1. write the address regsiter
-2. write the command register to read
-3. wait for interrupt or pool on status
-4. Check status for fault and number of bytes.
-5. read the data register for 512 bytes. (64 ld, or 128 lw)
-
-
-non dma write operation
-1. write address register
-2. write data register for 512 bytes. (64 sd, or 128 sw)
-3. write command register to write data to flash
-4. wait for interrupt or pool on status
-5. check status for fault and number of bytes written.
-
-implement dma transfers later
-
-
-interrupts
-1. operation done
-2. bus error (more of an exception)
-   Occurs if attempting to do an operation while the flash controller is busy.
-   ie. if status[31] is set generate an interrupt
-   This is tricky in a multiprocessor environment.
-
-
-
-
-tasks
-1. [-] Remove all AFRL identifiers
-2. [X] get the existing sdc compiled on wally.
-   1. [X] use wally primatives over tcore's
-3. build abhlite interface with the above registers and necessary fsm.
-   1. [ ]  The sd card reader uses a 4 bit data interface.  We can change this to be something
-      more pratical.
-4. write test programs
-5. [X] Convert VHDL to system verilog

pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv

@@ -25,14 +25,15 @@
 
 `include "wally-config.vh"
 
-module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
-  (input logic 		clk,
+module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WIDTH = 4) (
+  input  logic 		                    clk,
   input  logic 		                    we1,
   input  logic [DEPTH-1:0]            ra1,
   output logic [WIDTH-1:0]            rd1,
   output logic [(2**DEPTH)*WIDTH-1:0] Rd1All,   
   input  logic [DEPTH-1:0]            wa1,
-   input logic [WIDTH-1:0]  wd1);
+  input  logic [WIDTH-1:0]            wd1
+);
   
   logic [WIDTH-1:0] 	    regs [2**DEPTH-1:0];
   genvar 		    index;

pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv

@@ -25,14 +25,15 @@
 
 `include "wally-config.vh"
 
-module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)
-  (input logic 		clk,
+module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDTH = 4)(
+  input  logic 		          clk,
   input  logic 		          we1,
   input  logic [WIDTH-1:0]  we1bit,
   input  logic [DEPTH-1:0]  ra1,
   output logic [WIDTH-1:0]  rd1,
   input  logic [DEPTH-1:0]  wa1,
-   input logic [WIDTH-1:0]  wd1);
+  input  logic [WIDTH-1:0]  wd1
+);
   
   logic [WIDTH-1:0] 	    regs [2**DEPTH-1:0];
   integer 		    i;

pipelined/src/uncore/sdc/sd_clk_fsm.sv

@@ -35,8 +35,7 @@
 
 `include "wally-config.vh"
 
-module sd_clk_fsm
-  (
+module sd_clk_fsm (
   input  logic 	CLK,
   input  logic 	i_RST,
   (* mark_debug = "true" *)output logic o_DONE,
@@ -44,7 +43,8 @@ module sd_clk_fsm
   (* mark_debug = "true" *)input  logic i_FATAL_ERROR,
   (* mark_debug = "true" *)output logic o_HS_TO_INIT_CLK_DIVIDER_RST, // resets clock divider that is going from 50 MHz to 400 KHz
   (* mark_debug = "true" *)output logic o_SD_CLK_SELECTED, // which clock is selected ('0'=HS or '1'=init)
-   (* mark_debug = "true" *)output logic o_G_CLK_SD_EN);  // Turns gated clock (G_CLK_SD) off and on
+  (* mark_debug = "true" *)output logic o_G_CLK_SD_EN // Turns gated clock (G_CLK_SD) off and on
+);  
 
 
   logic [3:0] 	w_next_state;

pipelined/src/uncore/sdc/sd_cmd_fsm.sv

@@ -26,9 +26,7 @@
 
 `include "wally-config.vh"
 
-module sd_cmd_fsm
-  (
-
+module sd_cmd_fsm (
   input  logic CLK, // HS
   //i_SLOWER_CLK                          : in  std_logic;
   input  logic i_RST, // reset FSM,
@@ -67,7 +65,6 @@ module sd_cmd_fsm
   // RX Components
   input  logic i_SD_CMD_RX, // serial response input on SD_CMD
   output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
-
   input  logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
   input  logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
   output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
@@ -90,8 +87,6 @@ module sd_cmd_fsm
   input  logic LIMIT_SD_TIMERS
 );
 
-
-
   logic  [4:0]  w_next_state;
   (* mark_debug = "true" *) logic  [4:0]  r_curr_state;
   logic 	w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;

pipelined/src/uncore/sdc/sd_dat_fsm.sv

@@ -28,8 +28,7 @@
 
 `include "wally-config.vh"
 
-module sd_dat_fsm
-  (
+module sd_dat_fsm (
   input  logic 	CLK, // HS Clock (48 MHz)
   input  logic 	i_RST,
   // Timer module control

pipelined/src/uncore/sdc/sd_top.sv

@@ -26,8 +26,7 @@
 
 `include "wally-config.vh"
 
-module sd_top #(parameter g_COUNT_WIDTH = 8)
-  (
+module sd_top #(parameter g_COUNT_WIDTH = 8) (
   input  logic 			   CLK, // 1.2 GHz (1.0 GHz typical)
   input  logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
   // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!

pipelined/src/uncore/sdc/sd_top_wrapper.v

@@ -1,7 +1,6 @@
 
 
-module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
-  (
+module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8) (
   input 		     clk_in1_p,
   input 		     clk_in1_n,   
   input 		     a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)

pipelined/src/uncore/sdc/simple_timer.sv

@@ -26,13 +26,13 @@
 
 `include "wally-config.vh"
 
-module simple_timer #(parameter BUS_WIDTH = 4)
-  (
+module simple_timer #(parameter BUS_WIDTH = 4) (
   input  logic [BUS_WIDTH-1:0] VALUE,
   input  logic 		            START,
   output logic 	              FLAG,
   input  logic 		            RST,
-   input logic 		       CLK);
+  input  logic 		            CLK
+);
 
 
   logic [BUS_WIDTH-1:0]     count;

pipelined/src/uncore/sdc/sipo_generic_ce.sv

@@ -29,8 +29,8 @@
 
 `include "wally-config.vh"
 
-module sipo_generic_ce #(g_BUS_WIDTH)
-  (input logic clk,
+module sipo_generic_ce #(g_BUS_WIDTH) (
+  input  logic clk,
   input  logic rst,
   input  logic i_enable,                 // data valid, write to register
   input  logic i_message_bit,            // serial data

pipelined/src/uncore/sdc/up_down_counter.sv

@@ -26,15 +26,15 @@
 
 `include "wally-config.vh"
 
-module up_down_counter #(parameter integer WIDTH=32)
-  (
+module up_down_counter #(parameter integer WIDTH=32) (
   input  logic [WIDTH-1:0]  CountIn,
   output logic [WIDTH-1:0]  CountOut,
   input  logic 		          Load,
   input  logic 		          Enable,
   input  logic 		          UpDown,   
   input  logic 		          clk,
-   input logic 		    reset);
+  input  logic 		          reset
+);
 
   logic [WIDTH-1:0] NextCount;
   logic [WIDTH-1:0] CountP1;

pipelined/src/uncore/uartPC16550D.sv

@@ -13,6 +13,8 @@
 //   Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
 //   Timeout not ye implemented***
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/uart_apb.sv

@@ -8,6 +8,8 @@
 //          Emulates interface of Texas Instruments PC165550D
 //          Compatible with UART in Imperas Virtio model ***
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

pipelined/src/uncore/uncore.sv

@@ -7,6 +7,8 @@
 // Purpose: System-on-Chip components outside the core
 //          Memories, peripherals, external bus control
 // 
+// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University