diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index d28697e21..e168b2c15 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -42,8 +42,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   input logic [11:0]          NextAdr, // virtual address, but we only use the lower 12 bits.
   input logic [`PA_BITS-1:0]  PAdr, // physical address
   input logic [(`XLEN-1)/8:0] ByteMask,
-  input logic [WORDLEN-1:0]     FinalWriteData,
-  input logic                        FStore2,
+  input logic [WORDLEN-1:0]   FinalWriteData,
+  input logic                 FStore2,
   output logic                CacheCommitted,
   output logic                CacheStall,
    // to performance counters to cpu
diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv
index 43c50e882..b93062365 100644
--- a/pipelined/src/lsu/subwordwrite.sv
+++ b/pipelined/src/lsu/subwordwrite.sv
@@ -39,7 +39,10 @@ module subwordwrite (
 );
 
   // Compute byte masks
-  swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
+  //swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
+  // *** fix me.
+  swbytemaskword #(.WORDLEN(`XLEN)) 
+  swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));  
   
   // Replicate data for subword writes
   if (`XLEN == 64) begin:sww