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Ross Thompson 2023-01-19 14:18:46 -06:00
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pipelined/src/ifu/spill.sv
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@ -8,6 +8,8 @@
// cache line boundaries or if instruction address without a cache crosses // cache line boundaries or if instruction address without a cache crosses
// XLEN/8 boundary. // XLEN/8 boundary.
// //
// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University