From 40d62ec0d1f6826ea8775fc8f177ccf3be56beba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 19 Jan 2023 14:18:46 -0600 Subject: [PATCH] Formatting. --- pipelined/src/ifu/spill.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv index f94be990a..1cdcae988 100644 --- a/pipelined/src/ifu/spill.sv +++ b/pipelined/src/ifu/spill.sv @@ -7,6 +7,8 @@ // Purpose: allows the IFU to make extra memory request if instruction address crosses // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. +// +// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. //