Lint cleanup

This commit is contained in:
David Harris 2024-06-18 06:15:17 -07:00
parent cac67aae4f
commit 3fa37b0233
8 changed files with 20 additions and 9 deletions

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@ -131,5 +131,6 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
W64M, FIntDivResultM); W64M, FIntDivResultM);
end else end else
assign FIntDivResultM = IntDivResultM[P.XLEN-1:0]; assign FIntDivResultM = IntDivResultM[P.XLEN-1:0];
end end else
assign FIntDivResultM = '0;
endmodule endmodule

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@ -147,7 +147,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
assign DivXShifted = DivX; assign DivXShifted = DivX;
end end
end else begin end else begin
assign ISpecialCaseE = 1'b0; assign {ISpecialCaseE, IntResultBitsE} = '0;
end end
////////////////////////////////////////////////////// //////////////////////////////////////////////////////
@ -238,7 +238,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM); flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
if (P.XLEN==64) if (P.XLEN==64)
flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
end end else
assign {ALTBM, IntDivM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0;
endmodule endmodule

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@ -98,6 +98,8 @@ module mmu import cvw::*; #(parameter cvw_t P,
assign TLBHit = 1'b0; assign TLBHit = 1'b0;
assign TLBPageFault = 1'b0; assign TLBPageFault = 1'b0;
assign PBMemoryType = 2'b00; assign PBMemoryType = 2'b00;
assign UpdateDA = 1'b0;
assign TLBPAdr = '0;
end end
// If translation is occuring, select translated physical address from TLB // If translation is occuring, select translated physical address from TLB

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@ -271,6 +271,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign FRM_REGW = '0; assign FRM_REGW = '0;
assign CSRUReadValM = '0; assign CSRUReadValM = '0;
assign IllegalCSRUAccessM = 1'b1; assign IllegalCSRUAccessM = 1'b1;
assign WriteFRMM = 1'b0;
assign WriteFFLAGSM = 1'b0;
end end
if (P.ZICNTR_SUPPORTED) begin:counters if (P.ZICNTR_SUPPORTED) begin:counters

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@ -45,8 +45,10 @@ module csrm import cvw::*; #(parameter cvw_t P) (
output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
output logic [15:0] MEDELEG_REGW, output logic [15:0] MEDELEG_REGW,
output logic [11:0] MIDELEG_REGW, output logic [11:0] MIDELEG_REGW,
/* verilator lint_off UNDRIVEN */ // PMP registers are only used when PMP_ENTRIES > 0
output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
/* verilator lint_on UNDRIVEN */
output logic WriteMSTATUSM, WriteMSTATUSHM, output logic WriteMSTATUSM, WriteMSTATUSHM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
output logic [63:0] MENVCFG_REGW output logic [63:0] MENVCFG_REGW

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@ -112,7 +112,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
default: PRDATA <= '0; default: PRDATA <= '0;
endcase endcase
end end
always_ff @(posedge PCLK or negedge PRESETn) always_ff @(posedge PCLK)
if (~PRESETn) begin if (~PRESETn) begin
MSIP <= 1'b0; MSIP <= 1'b0;
MTIMECMP <= '0; MTIMECMP <= '0;
@ -131,7 +131,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
// eventually replace MTIME logic below with timereg // eventually replace MTIME logic below with timereg
// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done); // timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done);
always_ff @(posedge PCLK or negedge PRESETn) always_ff @(posedge PCLK)
if (~PRESETn) begin if (~PRESETn) begin
MTIME <= '0; MTIME <= '0;
// MTIMECMP is not reset // MTIMECMP is not reset

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@ -75,11 +75,14 @@ module uncore import cvw::*; #(parameter cvw_t P)(
logic SDCIntM; logic SDCIntM;
logic PCLK, PRESETn, PWRITE, PENABLE; logic PCLK, PRESETn, PWRITE, PENABLE;
logic [4:0] PSEL, PREADY; logic [4:0] PSEL;
logic [31:0] PADDR; logic [31:0] PADDR;
logic [P.XLEN-1:0] PWDATA; logic [P.XLEN-1:0] PWDATA;
logic [P.XLEN/8-1:0] PSTRB; logic [P.XLEN/8-1:0] PSTRB;
/* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration
logic [4:0] PREADY;
logic [4:0][P.XLEN-1:0] PRDATA; logic [4:0][P.XLEN-1:0] PRDATA;
/* verilator lint_on UNDRIVEN */
logic [P.XLEN-1:0] HREADBRIDGE; logic [P.XLEN-1:0] HREADBRIDGE;
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
@ -106,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)(
ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
end end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
if (P.BOOTROM_SUPPORTED) begin : bootrom if (P.BOOTROM_SUPPORTED) begin : bootrom
rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom)); .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
end end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
if (P.CLINT_SUPPORTED == 1) begin : clint if (P.CLINT_SUPPORTED == 1) begin : clint

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@ -353,7 +353,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.SetFflagsM, // FPU flags (to privileged unit) .SetFflagsM, // FPU flags (to privileged unit)
.FIntDivResultW); .FIntDivResultW);
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM,
IllegalFPUInstrD, SetFflagsM, FpLoadStoreM, IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0; FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0;
end end