From 3fa37b0233d120132bfbd559d88f669a78bddd36 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 18 Jun 2024 06:15:17 -0700 Subject: [PATCH] Lint cleanup --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 3 ++- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 5 +++-- src/mmu/mmu.sv | 2 ++ src/privileged/csr.sv | 2 ++ src/privileged/csrm.sv | 2 ++ src/uncore/clint_apb.sv | 4 ++-- src/uncore/uncore.sv | 9 ++++++--- src/wally/wallypipelinedcore.sv | 2 +- 8 files changed, 20 insertions(+), 9 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5bfb11b56..6a2830421 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -131,5 +131,6 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( W64M, FIntDivResultM); end else assign FIntDivResultM = IntDivResultM[P.XLEN-1:0]; - end + end else + assign FIntDivResultM = '0; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 1f668911a..afdb5cb92 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -147,7 +147,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign DivXShifted = DivX; end end else begin - assign ISpecialCaseE = 1'b0; + assign {ISpecialCaseE, IntResultBitsE} = '0; end ////////////////////////////////////////////////////// @@ -238,7 +238,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM); if (P.XLEN==64) flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); - end + end else + assign {ALTBM, IntDivM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0; endmodule diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index c9d4c3415..b7e8e44a8 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -98,6 +98,8 @@ module mmu import cvw::*; #(parameter cvw_t P, assign TLBHit = 1'b0; assign TLBPageFault = 1'b0; assign PBMemoryType = 2'b00; + assign UpdateDA = 1'b0; + assign TLBPAdr = '0; end // If translation is occuring, select translated physical address from TLB diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index a9d38028e..c6328a19c 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -271,6 +271,8 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign FRM_REGW = '0; assign CSRUReadValM = '0; assign IllegalCSRUAccessM = 1'b1; + assign WriteFRMM = 1'b0; + assign WriteFFLAGSM = 1'b0; end if (P.ZICNTR_SUPPORTED) begin:counters diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 7aaf4c052..58ca290e2 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -45,8 +45,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, output logic [15:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, + /* verilator lint_off UNDRIVEN */ // PMP registers are only used when PMP_ENTRIES > 0 output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], + /* verilator lint_on UNDRIVEN */ output logic WriteMSTATUSM, WriteMSTATUSHM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM, output logic [63:0] MENVCFG_REGW diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 41c9f47ef..76735aaa6 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -112,7 +112,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( default: PRDATA <= '0; endcase end - always_ff @(posedge PCLK or negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin MSIP <= 1'b0; MTIMECMP <= '0; @@ -131,7 +131,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( // eventually replace MTIME logic below with timereg // timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done); - always_ff @(posedge PCLK or negedge PRESETn) + always_ff @(posedge PCLK) if (~PRESETn) begin MTIME <= '0; // MTIMECMP is not reset diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 9390b35cf..39a2be09a 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -75,11 +75,14 @@ module uncore import cvw::*; #(parameter cvw_t P)( logic SDCIntM; logic PCLK, PRESETn, PWRITE, PENABLE; - logic [4:0] PSEL, PREADY; + logic [4:0] PSEL; logic [31:0] PADDR; logic [P.XLEN-1:0] PWDATA; logic [P.XLEN/8-1:0] PSTRB; + /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration + logic [4:0] PREADY; logic [4:0][P.XLEN-1:0] PRDATA; + /* verilator lint_on UNDRIVEN */ logic [P.XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; @@ -106,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)( ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); - end + end else assign {HREADRam, HRESPRam, HREADYRam} = '0; if (P.BOOTROM_SUPPORTED) begin : bootrom rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom)); - end + end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0; // memory-mapped I/O peripherals if (P.CLINT_SUPPORTED == 1) begin : clint diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 16a4d9e61..49d1f049c 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -353,7 +353,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .SetFflagsM, // FPU flags (to privileged unit) .FIntDivResultW); end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low - assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, + assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM, IllegalFPUInstrD, SetFflagsM, FpLoadStoreM, FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0; end