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Limnanthes Serafini 2023-04-12 02:57:42 -07:00
parent 095f3d5542
commit 3f9a22e8d4
2 changed files with 4 additions and 0 deletions
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1
bin/CacheSim.py
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@ -38,6 +38,7 @@
# With verbose mode on, the simulator logs each access into the cache. # With verbose mode on, the simulator logs each access into the cache.
# Add -p or --perf to report the hit/miss ratio. # Add -p or --perf to report the hit/miss ratio.
# Add -d or --dist to report the distribution of loads, stores, and atomic ops. # Add -d or --dist to report the distribution of loads, stores, and atomic ops.
# These distributions may not add up to 100; this is because of flushes or invalidations.
import sys import sys
import math import math

3
sim/rv64gc_CacheSim.py
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@ -32,6 +32,9 @@ import argparse
# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled! # NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
# This does not check the test output for correctness, run regression for that. # This does not check the test output for correctness, run regression for that.
# Add -p or --perf to report the hit/miss ratio.
# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
# These distributions may not add up to 100; this is because of flushes or invalidations.
class bcolors: class bcolors:
HEADER = '\033[95m' HEADER = '\033[95m'