diff --git a/bin/CacheSim.py b/bin/CacheSim.py
index d94d3e69f..7fd36b054 100755
--- a/bin/CacheSim.py
+++ b/bin/CacheSim.py
@@ -38,6 +38,7 @@
 # With verbose mode on, the simulator logs each access into the cache.
 # Add -p or --perf to report the hit/miss ratio. 
 # Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
 
 import sys
 import math
diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py
index 5811c6922..299281d5f 100755
--- a/sim/rv64gc_CacheSim.py
+++ b/sim/rv64gc_CacheSim.py
@@ -32,6 +32,9 @@ import argparse
 
 # NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
 # This does not check the test output for correctness, run regression for that.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
 
 class bcolors:
     HEADER = '\033[95m'