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Fixing latches.

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This commit is contained in:
Jacob Pease 2024-10-31 13:54:56 -05:00
parent 72a854eb07
commit 3ee5fffe02
2 changed files with 9 additions and 0 deletions
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1
src/uncore/spi_apb.sv
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@ -275,6 +275,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
START: NextState = WAIT; START: NextState = WAIT;
WAIT: if (TransmitFIFOReadEmpty & ~Transmitting & ~TransmitRegLoaded) NextState = READY; WAIT: if (TransmitFIFOReadEmpty & ~Transmitting & ~TransmitRegLoaded) NextState = READY;
else NextState = WAIT; else NextState = WAIT;
default: NextState = READY;
endcase endcase
end end

8
src/uncore/spi_controller.sv
View File

@ -296,6 +296,7 @@ module spi_controller (
AUTOMODE: begin AUTOMODE: begin
if (EndTransmission) NextState = INACTIVE; if (EndTransmission) NextState = INACTIVE;
else if (EndOfFrameDelay) NextState = SCKCS; else if (EndOfFrameDelay) NextState = SCKCS;
else NextState = TRANSMIT;
end end
HOLDMODE: begin HOLDMODE: begin
if (EndTransmission) NextState = HOLD; if (EndTransmission) NextState = HOLD;
@ -307,6 +308,7 @@ module spi_controller (
else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end end
default: NextState = TRANSMIT;
endcase endcase
end end
SCKCS: begin // SCKCS case -------------------------------------- SCKCS: begin // SCKCS case --------------------------------------
@ -318,6 +320,8 @@ module spi_controller (
if (HasINTERCS) NextState = INTERCS; if (HasINTERCS) NextState = INTERCS;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end end
end else begin
NextState = SCKCS;
end end
end end
HOLD: begin // HOLD mode case ----------------------------------- HOLD: begin // HOLD mode case -----------------------------------
@ -331,11 +335,15 @@ module spi_controller (
if (EndOfINTERCS) begin if (EndOfINTERCS) begin
if (HasCSSCK) NextState = CSSCK; if (HasCSSCK) NextState = CSSCK;
else NextState = TRANSMIT; else NextState = TRANSMIT;
end else begin
NextState = INTERCS;
end end
end end
INTERXFR: begin // INTERXFR case -------------------------------- INTERXFR: begin // INTERXFR case --------------------------------
if (EndOfINTERXFR) begin if (EndOfINTERXFR) begin
NextState = TRANSMIT; NextState = TRANSMIT;
end else begin
NextState = INTERXFR;
end end
end end
default: begin default: begin