mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:openhwgroup/cvw
This commit is contained in:
commit
3e891ee635
@ -1,5 +1,5 @@
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|||||||
//////////////////////////////////////////
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//////////////////////////////////////////
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||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
@ -25,9 +25,6 @@
|
|||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// include shared configuration
|
|
||||||
// `include "wally-shared.vh"
|
|
||||||
|
|
||||||
`include "BranchPredictorType.vh"
|
`include "BranchPredictorType.vh"
|
||||||
|
|
||||||
localparam FPGA = 0;
|
localparam FPGA = 0;
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
//////////////////////////////////////////
|
//////////////////////////////////////////
|
||||||
// wally-config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
|
@ -205,7 +205,7 @@ always @(posedge clock)
|
|||||||
reset_sync <= {reset_sync[1:0], !async_resetn};
|
reset_sync <= {reset_sync[1:0], !async_resetn};
|
||||||
|
|
||||||
reg [7:0] clock_cnt;
|
reg [7:0] clock_cnt;
|
||||||
reg clock_state;
|
(* mark_debug = "true" *) reg clock_state;
|
||||||
(* mark_debug = "true" *) reg clock_posedge;
|
(* mark_debug = "true" *) reg clock_posedge;
|
||||||
reg clock_data_in;
|
reg clock_data_in;
|
||||||
wire fifo_almost_full;
|
wire fifo_almost_full;
|
||||||
@ -265,7 +265,7 @@ wire sd_dat_oe;
|
|||||||
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
|
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
|
||||||
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
|
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
|
||||||
|
|
||||||
always @(negedge clock) begin
|
always @(negedge sdio_clk) begin
|
||||||
// Output data delayed by 1/2 clock cycle (5ns) to ensure
|
// Output data delayed by 1/2 clock cycle (5ns) to ensure
|
||||||
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
|
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
|
||||||
if (sdio_reset) begin
|
if (sdio_reset) begin
|
||||||
|
@ -56,7 +56,7 @@ done
|
|||||||
IMAGES=$BUILDROOT/output/images
|
IMAGES=$BUILDROOT/output/images
|
||||||
FW_JUMP=$IMAGES/fw_jump.bin
|
FW_JUMP=$IMAGES/fw_jump.bin
|
||||||
LINUX_KERNEL=$IMAGES/Image
|
LINUX_KERNEL=$IMAGES/Image
|
||||||
DEVICE_TREE=$IMAGES/$DEVICE_TREE
|
#DEVICE_TREE=$IMAGES/$DEVICE_TREE
|
||||||
|
|
||||||
SDCARD=${ARGS[0]}
|
SDCARD=${ARGS[0]}
|
||||||
|
|
||||||
|
@ -49,6 +49,7 @@ clean:
|
|||||||
riscoftests:
|
riscoftests:
|
||||||
# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
|
# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
|
||||||
make -C ../tests/riscof/
|
make -C ../tests/riscof/
|
||||||
|
|
||||||
memfiles:
|
memfiles:
|
||||||
make -f makefile-memfile wally-sim-files --jobs
|
make -f makefile-memfile wally-sim-files --jobs
|
||||||
|
|
||||||
|
@ -14,8 +14,14 @@
|
|||||||
--override cpu/add_implicit_Extensions=B
|
--override cpu/add_implicit_Extensions=B
|
||||||
--override cpu/bitmanip_version=1.0.0
|
--override cpu/bitmanip_version=1.0.0
|
||||||
|
|
||||||
# ????
|
# More extensions
|
||||||
--override cpu/Zicbom=T
|
--override cpu/Zicbom=T
|
||||||
|
--override cpu/Zicbop=T
|
||||||
|
--override cpu/Zicboz=T
|
||||||
|
--override cpu/Svpbmt=T
|
||||||
|
# 64 KiB continuous huge pages supported
|
||||||
|
--override cpu/Svnapot_page_mask=1<<16
|
||||||
|
|
||||||
|
|
||||||
# clarify
|
# clarify
|
||||||
#--override refRoot/cpu/mtvec_sext=F
|
#--override refRoot/cpu/mtvec_sext=F
|
||||||
|
@ -85,7 +85,7 @@ for test in tests64i:
|
|||||||
configs.append(tc)
|
configs.append(tc)
|
||||||
|
|
||||||
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
||||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
|
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
|
||||||
for test in tests32gc:
|
for test in tests32gc:
|
||||||
tc = TestCase(
|
tc = TestCase(
|
||||||
name=test,
|
name=test,
|
||||||
@ -133,7 +133,7 @@ for test in ahbTests:
|
|||||||
configs.append(tc)
|
configs.append(tc)
|
||||||
|
|
||||||
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||||
"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
|
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
|
||||||
if (coverage): # delete all but 64gc tests when running coverage
|
if (coverage): # delete all but 64gc tests when running coverage
|
||||||
configs = []
|
configs = []
|
||||||
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||||
|
@ -52,6 +52,8 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
|||||||
"arch64zi", "wally64a", "wally64periph", "wally64priv",
|
"arch64zi", "wally64a", "wally64periph", "wally64priv",
|
||||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||||
"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
||||||
|
# arch64i is the most interesting case. Uncomment line below to run just that case
|
||||||
|
tests64gc = ["arch64i"]
|
||||||
|
|
||||||
cachetypes = ["ICache", "DCache"]
|
cachetypes = ["ICache", "DCache"]
|
||||||
simdir = os.path.expanduser("~/cvw/sim")
|
simdir = os.path.expanduser("~/cvw/sim")
|
||||||
|
@ -1,2 +1,2 @@
|
|||||||
vsim -do "do wally.do rv64gc arch64d"
|
vsim -do "do wally.do rv64gc wally64priv"
|
||||||
|
|
||||||
|
@ -16,7 +16,7 @@ done
|
|||||||
echo "All lints run with no errors or warnings"
|
echo "All lints run with no errors or warnings"
|
||||||
|
|
||||||
# --lint-only just runs lint rather than trying to compile and simulate
|
# --lint-only just runs lint rather than trying to compile and simulate
|
||||||
# -I points to the include directory where files such as `include wally-config.vh are found
|
# -I points to the include directory where files such as `include config.vh are found
|
||||||
|
|
||||||
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
|
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
|
||||||
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
|
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
|
||||||
|
@ -40,7 +40,7 @@ vlog +incdir+../config/$1 \
|
|||||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
|
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
|
||||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
|
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
|
||||||
../src/cvw.sv \
|
../src/cvw.sv \
|
||||||
../testbench/testbench_imperas.sv \
|
../testbench/testbench-imperas.sv \
|
||||||
../testbench/common/*.sv \
|
../testbench/common/*.sv \
|
||||||
../src/*/*.sv \
|
../src/*/*.sv \
|
||||||
../src/*/*/*.sv \
|
../src/*/*/*.sv \
|
||||||
|
@ -24,7 +24,7 @@
|
|||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh"
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
module divshiftcalc import cvw::*; #(parameter cvw_t P) (
|
module divshiftcalc import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic [P.DIVb:0] DivQm, // divsqrt significand
|
input logic [P.DIVb:0] DivQm, // divsqrt significand
|
||||||
|
@ -51,6 +51,8 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
|
|||||||
logic Asign, Bsign; // Sign bits of A, B
|
logic Asign, Bsign; // Sign bits of A, B
|
||||||
|
|
||||||
// Addition
|
// Addition
|
||||||
|
// CondMaskB is B for add/sub, or a masked version of B for certain bit manipulation instructions
|
||||||
|
// CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
|
||||||
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
|
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
|
||||||
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
|
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
|
||||||
|
|
||||||
|
@ -145,7 +145,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
|
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
|
||||||
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
|
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
|
||||||
|
|
||||||
assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
|
assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID | CSRAdrM == MCONFIGPTR);
|
||||||
|
|
||||||
// CSRs
|
// CSRs
|
||||||
flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
|
flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
|
||||||
|
@ -27,7 +27,7 @@
|
|||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
`include "wally-config.vh"
|
`include "config.vh"
|
||||||
|
|
||||||
// This comparator is best
|
// This comparator is best
|
||||||
module comparator_dc_flip #(parameter WIDTH=64) (
|
module comparator_dc_flip #(parameter WIDTH=64) (
|
||||||
|
@ -26,7 +26,7 @@
|
|||||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wconfig.vh"
|
||||||
|
|
||||||
|
|
||||||
module sd_top_tb();
|
module sd_top_tb();
|
||||||
|
@ -265,10 +265,8 @@ module testbench;
|
|||||||
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
||||||
// the addr of each label and fill the array. To expand, add more elements to this array
|
// the addr of each label and fill the array. To expand, add more elements to this array
|
||||||
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
||||||
if(!P.FPGA) begin
|
|
||||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
||||||
end
|
end
|
||||||
end
|
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
// Verify the test ran correctly by checking the memory against a known signature.
|
// Verify the test ran correctly by checking the memory against a known signature.
|
||||||
@ -361,21 +359,21 @@ module testbench;
|
|||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
// load memories with program image
|
// load memories with program image
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator
|
if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator
|
||||||
if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
|
if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
|
||||||
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
|
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
|
||||||
if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
|
if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (LoadMem) begin
|
if (LoadMem) begin
|
||||||
if (P.FPGA) begin
|
if (P.SDC_SUPPORTED) begin
|
||||||
`ifdef TB_FPGA
|
`ifdef TB_SDC_SUPPORTED
|
||||||
string romfilename, sdcfilename;
|
string romfilename, sdcfilename;
|
||||||
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
||||||
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
||||||
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
|
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
|
||||||
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
||||||
// shorten sdc timers for simulation
|
// shorten sdc timers for simulation
|
||||||
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
else if (P.IROM_SUPPORTED) begin
|
else if (P.IROM_SUPPORTED) begin
|
||||||
|
@ -37,9 +37,9 @@ module testbench;
|
|||||||
parameter DEBUG=0;
|
parameter DEBUG=0;
|
||||||
parameter TEST="none";
|
parameter TEST="none";
|
||||||
parameter PrintHPMCounters=1;
|
parameter PrintHPMCounters=1;
|
||||||
parameter BPRED_LOGGER=0;
|
parameter BPRED_LOGGER=1;
|
||||||
parameter I_CACHE_ADDR_LOGGER=0;
|
parameter I_CACHE_ADDR_LOGGER=1;
|
||||||
parameter D_CACHE_ADDR_LOGGER=0;
|
parameter D_CACHE_ADDR_LOGGER=1;
|
||||||
|
|
||||||
`include "parameter-defs.vh"
|
`include "parameter-defs.vh"
|
||||||
|
|
||||||
@ -98,6 +98,7 @@ module testbench;
|
|||||||
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
|
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
|
||||||
else tests = {arch64c};
|
else tests = {arch64c};
|
||||||
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
|
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
|
||||||
|
"arch64a": if (P.A_SUPPORTED) tests = arch64a;
|
||||||
"arch64f": if (P.F_SUPPORTED) tests = arch64f;
|
"arch64f": if (P.F_SUPPORTED) tests = arch64f;
|
||||||
"arch64d": if (P.D_SUPPORTED) tests = arch64d;
|
"arch64d": if (P.D_SUPPORTED) tests = arch64d;
|
||||||
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
|
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
|
||||||
@ -131,6 +132,7 @@ module testbench;
|
|||||||
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
|
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
|
||||||
else tests = {arch32c};
|
else tests = {arch32c};
|
||||||
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
|
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
|
||||||
|
"arch32a": if (P.A_SUPPORTED) tests = arch32a;
|
||||||
"arch32f": if (P.F_SUPPORTED) tests = arch32f;
|
"arch32f": if (P.F_SUPPORTED) tests = arch32f;
|
||||||
"arch32d": if (P.D_SUPPORTED) tests = arch32d;
|
"arch32d": if (P.D_SUPPORTED) tests = arch32d;
|
||||||
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
|
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
|
||||||
@ -260,10 +262,8 @@ module testbench;
|
|||||||
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
||||||
// the addr of each label and fill the array. To expand, add more elements to this array
|
// the addr of each label and fill the array. To expand, add more elements to this array
|
||||||
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
||||||
if(!P.FPGA) begin
|
|
||||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
||||||
end
|
end
|
||||||
end
|
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
// Verify the test ran correctly by checking the memory against a known signature.
|
// Verify the test ran correctly by checking the memory against a known signature.
|
||||||
@ -344,14 +344,14 @@ module testbench;
|
|||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (LoadMem) begin
|
if (LoadMem) begin
|
||||||
if (P.FPGA) begin
|
if (P.SDC_SUPPORTED) begin
|
||||||
string romfilename, sdcfilename;
|
string romfilename, sdcfilename;
|
||||||
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
||||||
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
||||||
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
|
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
|
||||||
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
||||||
// shorten sdc timers for simulation
|
// shorten sdc timers for simulation
|
||||||
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
||||||
end
|
end
|
||||||
else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
||||||
else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||||
@ -377,7 +377,7 @@ module testbench;
|
|||||||
assign {HRESPEXT, HRDATAEXT} = '0;
|
assign {HRESPEXT, HRDATAEXT} = '0;
|
||||||
end
|
end
|
||||||
|
|
||||||
if(P.FPGA) begin : sdcard
|
if(P.SDC_SUPPORTED) begin : sdcard
|
||||||
// *** fix later
|
// *** fix later
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
sdModel sdcard
|
sdModel sdcard
|
||||||
@ -395,7 +395,7 @@ module testbench;
|
|||||||
assign SDCIntr = '0;
|
assign SDCIntr = '0;
|
||||||
end
|
end
|
||||||
|
|
||||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
|
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
|
||||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||||
.UARTSin, .UARTSout, .SDCIntr);
|
.UARTSin, .UARTSout, .SDCIntr);
|
||||||
|
@ -864,13 +864,11 @@ string imperas32f[] = '{
|
|||||||
|
|
||||||
string wally64a[] = '{
|
string wally64a[] = '{
|
||||||
`WALLYTEST,
|
`WALLYTEST,
|
||||||
"rv64i_m/privilege/src/WALLY-amo-01.S",
|
|
||||||
"rv64i_m/privilege/src/WALLY-lrsc-01.S"
|
"rv64i_m/privilege/src/WALLY-lrsc-01.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
string wally32a[] = '{
|
string wally32a[] = '{
|
||||||
`WALLYTEST,
|
`WALLYTEST,
|
||||||
"rv32i_m/privilege/src/WALLY-amo-01.S",
|
|
||||||
"rv32i_m/privilege/src/WALLY-lrsc-01.S"
|
"rv32i_m/privilege/src/WALLY-lrsc-01.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -902,6 +900,20 @@ string imperas32f[] = '{
|
|||||||
"rv64i_m/Zifencei/src/Fencei.S"
|
"rv64i_m/Zifencei/src/Fencei.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
string arch32a[] = '{
|
||||||
|
`RISCVARCHTEST,
|
||||||
|
"rv32i_m/A/src/amoadd.w-01.S",
|
||||||
|
"rv32i_m/A/src/amoand.w-01.S",
|
||||||
|
"rv32i_m/A/src/amomax.w-01.S",
|
||||||
|
"rv32i_m/A/src/amomaxu.w-01.S",
|
||||||
|
"rv32i_m/A/src/amomin.w-01.S",
|
||||||
|
"rv32i_m/A/src/amominu.w-01.S",
|
||||||
|
"rv32i_m/A/src/amoor.w-01.S",
|
||||||
|
"rv32i_m/A/src/amoswap.w-01.S",
|
||||||
|
"rv32i_m/A/src/amoxor.w-01.S"
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
string arch32zi[] = '{
|
string arch32zi[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
"rv32i_m/Zifencei/src/Fencei.S"
|
"rv32i_m/Zifencei/src/Fencei.S"
|
||||||
@ -972,6 +984,28 @@ string imperas32f[] = '{
|
|||||||
"rv64i_m/M/src/remw-01.S"
|
"rv64i_m/M/src/remw-01.S"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
string arch64a[] = '{
|
||||||
|
`RISCVARCHTEST,
|
||||||
|
"rv64i_m/A/src/amoadd.w-01.S",
|
||||||
|
"rv64i_m/A/src/amoand.w-01.S",
|
||||||
|
"rv64i_m/A/src/amomax.w-01.S",
|
||||||
|
"rv64i_m/A/src/amomaxu.w-01.S",
|
||||||
|
"rv64i_m/A/src/amomin.w-01.S",
|
||||||
|
"rv64i_m/A/src/amominu.w-01.S",
|
||||||
|
"rv64i_m/A/src/amoor.w-01.S",
|
||||||
|
"rv64i_m/A/src/amoswap.w-01.S",
|
||||||
|
"rv64i_m/A/src/amoxor.w-01.S",
|
||||||
|
"rv64i_m/A/src/amoadd.d-01.S",
|
||||||
|
"rv64i_m/A/src/amoand.d-01.S",
|
||||||
|
"rv64i_m/A/src/amomax.d-01.S",
|
||||||
|
"rv64i_m/A/src/amomaxu.d-01.S",
|
||||||
|
"rv64i_m/A/src/amomin.d-01.S",
|
||||||
|
"rv64i_m/A/src/amominu.d-01.S",
|
||||||
|
"rv64i_m/A/src/amoor.d-01.S",
|
||||||
|
"rv64i_m/A/src/amoswap.d-01.S",
|
||||||
|
"rv64i_m/A/src/amoxor.d-01.S"
|
||||||
|
};
|
||||||
|
|
||||||
string arch64c[] = '{
|
string arch64c[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
"rv64i_m/C/src/cadd-01.S",
|
"rv64i_m/C/src/cadd-01.S",
|
||||||
@ -1936,6 +1970,7 @@ string arch64zbs[] = '{
|
|||||||
|
|
||||||
string wally64priv[] = '{
|
string wally64priv[] = '{
|
||||||
`WALLYTEST,
|
`WALLYTEST,
|
||||||
|
"rv64i_m/privilege/src/WALLY-minfo-01.S",
|
||||||
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
|
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
|
||||||
"rv64i_m/privilege/src/WALLY-cboz-01.S",
|
"rv64i_m/privilege/src/WALLY-cboz-01.S",
|
||||||
"rv64i_m/privilege/src/WALLY-cbom-01.S",
|
"rv64i_m/privilege/src/WALLY-cbom-01.S",
|
||||||
|
@ -57,6 +57,8 @@ class sail_cSim(pluginTemplate):
|
|||||||
self.isa += 'i'
|
self.isa += 'i'
|
||||||
if "M" in ispec["ISA"]:
|
if "M" in ispec["ISA"]:
|
||||||
self.isa += 'm'
|
self.isa += 'm'
|
||||||
|
if "A" in ispec["ISA"]:
|
||||||
|
self.isa += 'a'
|
||||||
if "C" in ispec["ISA"]:
|
if "C" in ispec["ISA"]:
|
||||||
self.isa += 'c'
|
self.isa += 'c'
|
||||||
if "F" in ispec["ISA"]:
|
if "F" in ispec["ISA"]:
|
||||||
|
@ -99,6 +99,8 @@ class spike(pluginTemplate):
|
|||||||
self.isa += 'i'
|
self.isa += 'i'
|
||||||
if "M" in ispec["ISA"]:
|
if "M" in ispec["ISA"]:
|
||||||
self.isa += 'm'
|
self.isa += 'm'
|
||||||
|
if "A" in ispec["ISA"]:
|
||||||
|
self.isa += 'a'
|
||||||
if "F" in ispec["ISA"]:
|
if "F" in ispec["ISA"]:
|
||||||
self.isa += 'f'
|
self.isa += 'f'
|
||||||
if "D" in ispec["ISA"]:
|
if "D" in ispec["ISA"]:
|
||||||
|
@ -29,19 +29,18 @@
|
|||||||
|
|
||||||
rv32i_sc_tests = \
|
rv32i_sc_tests = \
|
||||||
WALLY-mmu-sv32 \
|
WALLY-mmu-sv32 \
|
||||||
WALLY-pmp \
|
WALLY-pm-01 \
|
||||||
WALLY-csr-permission-s-01 \
|
WALLY-csr-permission-s-01 \
|
||||||
WALLY-csr-permission-u-01 \
|
WALLY-csr-permission-u-01 \
|
||||||
WALLY-minfo-01 \
|
|
||||||
WALLY-misa-01 \
|
WALLY-misa-01 \
|
||||||
WALLY-amo \
|
WALLY-lrsc-01 \
|
||||||
WALLY-lrsc \
|
|
||||||
WALLY-status-mie-01 \
|
WALLY-status-mie-01 \
|
||||||
WALLY-trap-sret-01 \
|
WALLY-trap-sret-01 \
|
||||||
|
|
||||||
|
|
||||||
target_tests_nosim = \
|
target_tests_nosim = \
|
||||||
WALLY-pma \
|
WALLY-pma-01 \
|
||||||
|
WALLY-minfo-01 \
|
||||||
WALLY-mtvec-01 \
|
WALLY-mtvec-01 \
|
||||||
WALLY-stvec-01 \
|
WALLY-stvec-01 \
|
||||||
WALLY-mie-01 \
|
WALLY-mie-01 \
|
||||||
|
@ -1,20 +0,0 @@
|
|||||||
fffffffe
|
|
||||||
00000001
|
|
||||||
fffffffb
|
|
||||||
fffffffd
|
|
||||||
ffffffef
|
|
||||||
000007ef
|
|
||||||
ffffffbf
|
|
||||||
ffffffff
|
|
||||||
fffffeff
|
|
||||||
fffffd7e
|
|
||||||
fffffeff
|
|
||||||
000007ff
|
|
||||||
ffffefff
|
|
||||||
ffffefff
|
|
||||||
ffffefff
|
|
||||||
ffffefff
|
|
||||||
fffeffff
|
|
||||||
000007fa
|
|
||||||
ffffffff
|
|
||||||
ffffffff
|
|
@ -110,9 +110,15 @@
|
|||||||
00000002 # S mode write to mhartid with illegal instruction
|
00000002 # S mode write to mhartid with illegal instruction
|
||||||
00000002 # S mode read from mhartid with illegal instruction
|
00000002 # S mode read from mhartid with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # S mode write to mconfigptr with illegal instruction
|
||||||
|
00000002 # S mode read from mconfigptr with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # S mode write to mstatus with illegal instruction
|
00000002 # S mode write to mstatus with illegal instruction
|
||||||
00000002 # S mode read from mstatus with illegal instruction
|
00000002 # S mode read from mstatus with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # S mode write to mstatush with illegal instruction
|
||||||
|
00000002 # S mode read from mstatush with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # S mode write to misa with illegal instruction
|
00000002 # S mode write to misa with illegal instruction
|
||||||
00000002 # S mode read from misa with illegal instruction
|
00000002 # S mode read from misa with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
@ -146,6 +152,15 @@
|
|||||||
00000002 # S mode write to mip with illegal instruction
|
00000002 # S mode write to mip with illegal instruction
|
||||||
00000002 # S mode read from mip with illegal instruction
|
00000002 # S mode read from mip with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # S mode write to menvcfg with illegal instruction
|
||||||
|
00000002 # S mode read from menvcfg with illegal instruction
|
||||||
|
00000bad
|
||||||
|
00000002 # S mode write to menvcfgh with illegal instruction
|
||||||
|
00000002 # S mode read from menvcfgh with illegal instruction
|
||||||
|
00000bad
|
||||||
|
00000002 # S mode write to mseccfg with illegal instruction
|
||||||
|
00000002 # S mode read from mseccfg with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # S mode write to pmpcfg0 with illegal instruction
|
00000002 # S mode write to pmpcfg0 with illegal instruction
|
||||||
00000002 # S mode read from pmpcfg0 with illegal instruction
|
00000002 # S mode read from pmpcfg0 with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
@ -41,9 +41,15 @@
|
|||||||
00000002 # U mode write to mhartid with illegal instruction
|
00000002 # U mode write to mhartid with illegal instruction
|
||||||
00000002 # U mode read from mhartid with illegal instruction
|
00000002 # U mode read from mhartid with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # S mode write to mconfigptr with illegal instruction
|
||||||
|
00000002 # S mode read from mconfigptr with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # U mode write to mstatus with illegal instruction
|
00000002 # U mode write to mstatus with illegal instruction
|
||||||
00000002 # U mode read from mstatus with illegal instruction
|
00000002 # U mode read from mstatus with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # U mode write to mstatush with illegal instruction
|
||||||
|
00000002 # U mode read from mstatush with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # U mode write to misa with illegal instruction
|
00000002 # U mode write to misa with illegal instruction
|
||||||
00000002 # U mode read from misa with illegal instruction
|
00000002 # U mode read from misa with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
@ -77,6 +83,18 @@
|
|||||||
00000002 # U mode write to mip with illegal instruction
|
00000002 # U mode write to mip with illegal instruction
|
||||||
00000002 # U mode read from mip with illegal instruction
|
00000002 # U mode read from mip with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
00000002 # S mode write to menvcfg with illegal instruction
|
||||||
|
00000002 # S mode read from menvcfg with illegal instruction
|
||||||
|
00000bad
|
||||||
|
00000002 # S mode write to menvcfgh with illegal instruction
|
||||||
|
00000002 # S mode read from menvcfgh with illegal instruction
|
||||||
|
00000bad
|
||||||
|
00000002 # S mode write to mseccfg with illegal instruction
|
||||||
|
00000002 # S mode read from mseccfg with illegal instruction
|
||||||
|
00000bad
|
||||||
|
00000002 # S mode write to senvcfg with illegal instruction
|
||||||
|
00000002 # S mode read from senvcfg with illegal instruction
|
||||||
|
00000bad
|
||||||
00000002 # U mode write to pmpcfg0 with illegal instruction
|
00000002 # U mode write to pmpcfg0 with illegal instruction
|
||||||
00000002 # U mode read from pmpcfg0 with illegal instruction
|
00000002 # U mode read from pmpcfg0 with illegal instruction
|
||||||
00000bad
|
00000bad
|
||||||
|
@ -6,4 +6,7 @@
|
|||||||
00000011 # confirm read-only permissions of mimpid
|
00000011 # confirm read-only permissions of mimpid
|
||||||
00000002 # write to read-only CSR failed with illegal instruction
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
00000011 # confirm read-only permissions of mhartid
|
00000011 # confirm read-only permissions of mhartid
|
||||||
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
|
00000011 # confirm read-only permissions of mconfigptr
|
||||||
0000000b # ecall from terminating tests in M mode
|
0000000b # ecall from terminating tests in M mode
|
||||||
|
|
||||||
|
@ -1,175 +0,0 @@
|
|||||||
///////////////////////////////////////////
|
|
||||||
// WALLY-AMO.S
|
|
||||||
//
|
|
||||||
// Tests Atomic AMO instructions
|
|
||||||
//
|
|
||||||
// David_Harris@hmc.edu 11 March 2021
|
|
||||||
//
|
|
||||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
// Adapted from Imperas RISCV-TEST_SUITE
|
|
||||||
//
|
|
||||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
|
||||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
|
||||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
|
||||||
// is furnished to do so, subject to the following conditions:
|
|
||||||
//
|
|
||||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
|
||||||
//
|
|
||||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
||||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
|
||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
///////////////////////////////////////////
|
|
||||||
|
|
||||||
#include "model_test.h"
|
|
||||||
#include "arch_test.h"
|
|
||||||
|
|
||||||
RVTEST_ISA("RV32IAF")
|
|
||||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo)
|
|
||||||
|
|
||||||
.section .text.init
|
|
||||||
.globl rvtest_entry_point
|
|
||||||
rvtest_entry_point:
|
|
||||||
RVMODEL_BOOT
|
|
||||||
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
# address for test results
|
|
||||||
la x6, wally_signature
|
|
||||||
la x31, test_data
|
|
||||||
|
|
||||||
# Testcase 0: amoswap.w
|
|
||||||
li x7, 1
|
|
||||||
amoswap.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffffffe (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be 00000001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 1: amoadd.w
|
|
||||||
li x7, 2
|
|
||||||
amoadd.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffffffb (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be fffffffd (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 2: amoand.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amoand.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be ffffffef (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be 000007ef (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 3: amoor.w
|
|
||||||
li x7, 0x44
|
|
||||||
amoor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be ffffffbf (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be ffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 4: amoxor.w
|
|
||||||
li x7, 0x381
|
|
||||||
amoxor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffffeff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be fffffd7e (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 5: amomax.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amomax.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffffeff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be 000007ff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 6: amomin.w
|
|
||||||
li x7, 0x7fd
|
|
||||||
amomin.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be ffffefff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be ffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 7: amomaxu.w
|
|
||||||
li x7, 0x7fb
|
|
||||||
amomaxu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be ffffefff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be ffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 8: amominu.w
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffeffff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be 000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
RVMODEL_HALT
|
|
||||||
|
|
||||||
RVTEST_DATA_BEGIN
|
|
||||||
.align 8
|
|
||||||
test_data:
|
|
||||||
.dword 0xfffffffdfffffffe
|
|
||||||
.dword 0xfffffff7fffffffb
|
|
||||||
.dword 0xffffffdfffffffef
|
|
||||||
.dword 0xffffff7fffffffbf
|
|
||||||
.dword 0xfffffdfffffffeff
|
|
||||||
.dword 0xfffff7fffffffeff
|
|
||||||
.dword 0x0fffdfffffffefff
|
|
||||||
.dword 0xffff7fffffffefff
|
|
||||||
.dword 0x3ffdfffffffeffff
|
|
||||||
.dword 0xfff7fffffffbffff
|
|
||||||
.dword 0xffdfffffffefffff
|
|
||||||
.dword 0xff7fffffffbfffff
|
|
||||||
.dword 0xfdfffffffeffffff
|
|
||||||
.dword 0xf7fffffffeffffff
|
|
||||||
.dword 0xdfffffffefffffff
|
|
||||||
.dword 0x7fffffffefffffff
|
|
||||||
.dword 0x00000001ffffffff
|
|
||||||
.dword 0x0000000400000002
|
|
||||||
.dword 0x0000001000000008
|
|
||||||
.dword 0x0000004000000020
|
|
||||||
.dword 0x0000010000000080
|
|
||||||
.dword 0x0000040000000200
|
|
||||||
.dword 0x0000100000000800
|
|
||||||
.dword 0x0000400000002000
|
|
||||||
.dword 0x0000000100008000
|
|
||||||
.dword 0x0004000000000002
|
|
||||||
.dword 0x0000001000080000
|
|
||||||
.dword 0x0040000000000020
|
|
||||||
.dword 0x0000010000800000
|
|
||||||
.dword 0x0400000000000200
|
|
||||||
.dword 0x0000100008000000
|
|
||||||
.dword 0x4000000000002000
|
|
||||||
.dword 0x0000000080000000
|
|
||||||
|
|
||||||
#ifdef rvtest_mtrap_routine
|
|
||||||
mtrap_sigptr:
|
|
||||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef rvtest_gpr_save
|
|
||||||
gpr_save:
|
|
||||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
RVTEST_DATA_END
|
|
||||||
|
|
||||||
RVMODEL_DATA_BEGIN
|
|
||||||
# signature output
|
|
||||||
wally_signature:
|
|
||||||
.fill 20, 4, -1
|
|
||||||
RVMODEL_DATA_END
|
|
@ -83,10 +83,11 @@ WRITE_READ_CSR mvendorid, 0x111
|
|||||||
WRITE_READ_CSR marchid, 0x111
|
WRITE_READ_CSR marchid, 0x111
|
||||||
WRITE_READ_CSR mimpid, 0x111
|
WRITE_READ_CSR mimpid, 0x111
|
||||||
WRITE_READ_CSR mhartid, 0x111
|
WRITE_READ_CSR mhartid, 0x111
|
||||||
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
WRITE_READ_CSR mconfigptr, 0x111
|
||||||
|
|
||||||
# Machine Trap Setup
|
# Machine Trap Setup
|
||||||
WRITE_READ_CSR mstatus, 0x111
|
WRITE_READ_CSR mstatus, 0x111
|
||||||
|
WRITE_READ_CSR mstatush, 0x111
|
||||||
WRITE_READ_CSR misa, 0x111
|
WRITE_READ_CSR misa, 0x111
|
||||||
WRITE_READ_CSR medeleg, 0x111
|
WRITE_READ_CSR medeleg, 0x111
|
||||||
WRITE_READ_CSR mideleg, 0x111
|
WRITE_READ_CSR mideleg, 0x111
|
||||||
@ -100,12 +101,11 @@ WRITE_READ_CSR mepc, 0x111
|
|||||||
WRITE_READ_CSR mcause, 0x111
|
WRITE_READ_CSR mcause, 0x111
|
||||||
WRITE_READ_CSR mtval, 0x111
|
WRITE_READ_CSR mtval, 0x111
|
||||||
WRITE_READ_CSR mip, 0x111
|
WRITE_READ_CSR mip, 0x111
|
||||||
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
|
|
||||||
# WRITE_READ_CSR mtval2, 0x111
|
|
||||||
|
|
||||||
# Machine Configuration
|
# Machine Configuration
|
||||||
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
|
WRITE_READ_CSR menvcfg, 0x111
|
||||||
# WRITE_READ_CSR mseccgf, 0x111
|
WRITE_READ_CSR menvcfgh, 0x111
|
||||||
|
WRITE_READ_CSR mseccfg, 0x111
|
||||||
|
|
||||||
# Machine Memory Protection
|
# Machine Memory Protection
|
||||||
WRITE_READ_CSR pmpcfg0, 0x111
|
WRITE_READ_CSR pmpcfg0, 0x111
|
||||||
|
@ -61,10 +61,11 @@ WRITE_READ_CSR mvendorid, 0xAAA
|
|||||||
WRITE_READ_CSR marchid, 0xAAA
|
WRITE_READ_CSR marchid, 0xAAA
|
||||||
WRITE_READ_CSR mimpid, 0xAAA
|
WRITE_READ_CSR mimpid, 0xAAA
|
||||||
WRITE_READ_CSR mhartid, 0xAAA
|
WRITE_READ_CSR mhartid, 0xAAA
|
||||||
# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
|
WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||||
|
|
||||||
# Machine Trap Setup
|
# Machine Trap Setup
|
||||||
WRITE_READ_CSR mstatus, 0xAAA
|
WRITE_READ_CSR mstatus, 0xAAA
|
||||||
|
WRITE_READ_CSR mstatush, 0xAAA
|
||||||
WRITE_READ_CSR misa, 0xAAA
|
WRITE_READ_CSR misa, 0xAAA
|
||||||
WRITE_READ_CSR medeleg, 0xAAA
|
WRITE_READ_CSR medeleg, 0xAAA
|
||||||
WRITE_READ_CSR mideleg, 0xAAA
|
WRITE_READ_CSR mideleg, 0xAAA
|
||||||
@ -78,12 +79,12 @@ WRITE_READ_CSR mepc, 0xAAA
|
|||||||
WRITE_READ_CSR mcause, 0xAAA
|
WRITE_READ_CSR mcause, 0xAAA
|
||||||
WRITE_READ_CSR mtval, 0xAAA
|
WRITE_READ_CSR mtval, 0xAAA
|
||||||
WRITE_READ_CSR mip, 0xAAA
|
WRITE_READ_CSR mip, 0xAAA
|
||||||
# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
|
|
||||||
# WRITE_READ_CSR mtval2, 0xAAA
|
|
||||||
|
|
||||||
# Machine Configuration
|
# Machine Configuration
|
||||||
# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
|
WRITE_READ_CSR menvcfg, 0xAAA
|
||||||
# WRITE_READ_CSR mseccgf, 0xAAA
|
WRITE_READ_CSR menvcfgh, 0xAAA
|
||||||
|
WRITE_READ_CSR senvcfg, 0xAAA
|
||||||
|
WRITE_READ_CSR mseccfg, 0xAAA
|
||||||
|
|
||||||
# Machine Memory Protection
|
# Machine Memory Protection
|
||||||
WRITE_READ_CSR pmpcfg0, 0xAAA
|
WRITE_READ_CSR pmpcfg0, 0xAAA
|
||||||
|
@ -24,7 +24,7 @@
|
|||||||
#include "WALLY-TEST-LIB-32.h"
|
#include "WALLY-TEST-LIB-32.h"
|
||||||
|
|
||||||
RVTEST_ISA("RV32I_Zicsr")
|
RVTEST_ISA("RV32I_Zicsr")
|
||||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
|
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",minfo)
|
||||||
|
|
||||||
INIT_TESTS
|
INIT_TESTS
|
||||||
|
|
||||||
@ -35,7 +35,7 @@ CSR_R_ACCESS mvendorid
|
|||||||
CSR_R_ACCESS marchid
|
CSR_R_ACCESS marchid
|
||||||
CSR_R_ACCESS mimpid
|
CSR_R_ACCESS mimpid
|
||||||
CSR_R_ACCESS mhartid
|
CSR_R_ACCESS mhartid
|
||||||
# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
|
CSR_R_ACCESS mconfigptr
|
||||||
|
|
||||||
END_TESTS
|
END_TESTS
|
||||||
|
|
||||||
|
@ -28,15 +28,13 @@
|
|||||||
# Description: Makefrag for RV64I architectural tests
|
# Description: Makefrag for RV64I architectural tests
|
||||||
|
|
||||||
rv64i_sc_tests = \
|
rv64i_sc_tests = \
|
||||||
WALLY-mmu-sv39 \
|
WALLY-mmu-sv39-01 \
|
||||||
WALLY-mmu-sv48 \
|
WALLY-mmu-sv48-01 \
|
||||||
WALLY-pmp \
|
WALLY-pmp-01 \
|
||||||
WALLY-minfo-01 \
|
|
||||||
WALLY-csr-permission-s-01 \
|
WALLY-csr-permission-s-01 \
|
||||||
WALLY-csr-permission-u-01 \
|
WALLY-csr-permission-u-01 \
|
||||||
WALLY-misa-01 \
|
WALLY-misa-01 \
|
||||||
WALLY-amo \
|
WALLY-lrsc-01 \
|
||||||
WALLY-lrsc \
|
|
||||||
WALLY-trap-sret-01 \
|
WALLY-trap-sret-01 \
|
||||||
WALLY-status-mie-01 \
|
WALLY-status-mie-01 \
|
||||||
WALLY-status-sie-01 \
|
WALLY-status-sie-01 \
|
||||||
@ -45,8 +43,9 @@ rv64i_sc_tests = \
|
|||||||
|
|
||||||
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
||||||
target_tests_nosim = \
|
target_tests_nosim = \
|
||||||
WALLY-pma \
|
WALLY-pma-01 \
|
||||||
WALLY-periph \
|
WALLY-minfo-01 \
|
||||||
|
WALLY-periph-01 \
|
||||||
WALLY-mtvec-01 \
|
WALLY-mtvec-01 \
|
||||||
WALLY-stvec-01 \
|
WALLY-stvec-01 \
|
||||||
WALLY-mie-01 \
|
WALLY-mie-01 \
|
||||||
@ -59,7 +58,11 @@ target_tests_nosim = \
|
|||||||
WALLY-cbom-01 \
|
WALLY-cbom-01 \
|
||||||
WALLY-cboz-01 \
|
WALLY-cboz-01 \
|
||||||
|
|
||||||
|
|
||||||
# unclear why status-fp-enabled and wfi aren't simulating ok
|
# unclear why status-fp-enabled and wfi aren't simulating ok
|
||||||
|
# DH 10/9/23: minfo needs Privileged Spec 1.12 for the mconfigptr register, but
|
||||||
|
# we don't have the right ISA string so it's compiling at 1.11
|
||||||
|
# and Sail throws an illegal instruction exception on csrr mconfigptr
|
||||||
|
|
||||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||||
|
|
||||||
|
@ -1,72 +0,0 @@
|
|||||||
fffffffe
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
00000000
|
|
||||||
fffffffb
|
|
||||||
ffffffff
|
|
||||||
fffffffd
|
|
||||||
ffffffff
|
|
||||||
ffffffef
|
|
||||||
ffffffff
|
|
||||||
000007ef
|
|
||||||
00000000
|
|
||||||
ffffffbf
|
|
||||||
ffffffff
|
|
||||||
ffffffff
|
|
||||||
ffffffff
|
|
||||||
fffffeff
|
|
||||||
ffffffff
|
|
||||||
fffffd7e
|
|
||||||
ffffffff
|
|
||||||
fffffeff
|
|
||||||
ffffffff
|
|
||||||
000007ff
|
|
||||||
00000000
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
fffeffff
|
|
||||||
ffffffff
|
|
||||||
000007fa
|
|
||||||
00000000
|
|
||||||
fffbffff
|
|
||||||
fff7ffff
|
|
||||||
00000001
|
|
||||||
00000000
|
|
||||||
ffefffff
|
|
||||||
ffdfffff
|
|
||||||
fff00001
|
|
||||||
ffdfffff
|
|
||||||
ffbfffff
|
|
||||||
ff7fffff
|
|
||||||
000007cf
|
|
||||||
00000000
|
|
||||||
feffffff
|
|
||||||
fdffffff
|
|
||||||
ffffffff
|
|
||||||
fdffffff
|
|
||||||
feffffff
|
|
||||||
f7ffffff
|
|
||||||
fefffc7e
|
|
||||||
f7ffffff
|
|
||||||
efffffff
|
|
||||||
dfffffff
|
|
||||||
000007ff
|
|
||||||
00000000
|
|
||||||
efffffff
|
|
||||||
7fffffff
|
|
||||||
000007fd
|
|
||||||
00000000
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
00000002
|
|
||||||
00000004
|
|
||||||
000007fa
|
|
||||||
00000000
|
|
@ -24,6 +24,12 @@
|
|||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
|
00000002 # S mode write to mconfigptr with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from mconfigptr with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
00000002 # S mode write to mstatus with illegal instruction
|
00000002 # S mode write to mstatus with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000002 # S mode read from mstatus with illegal instruction
|
00000002 # S mode read from mstatus with illegal instruction
|
||||||
@ -96,6 +102,18 @@
|
|||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
|
00000002 # S mode write to menvcfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from menvcfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
|
00000002 # S mode write to mseccfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from mseccfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
00000002 # S mode write to pmpcfg0 with illegal instruction
|
00000002 # S mode write to pmpcfg0 with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000002 # S mode read from pmpcfg0 with illegal instruction
|
00000002 # S mode read from pmpcfg0 with illegal instruction
|
||||||
|
@ -84,6 +84,12 @@
|
|||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
|
00000002 # S mode write to mconfigptr with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from mconfigptr with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
00000002 # U mode write to mstatus with illegal instruction
|
00000002 # U mode write to mstatus with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000002 # U mode read from mstatus with illegal instruction
|
00000002 # U mode read from mstatus with illegal instruction
|
||||||
@ -156,6 +162,18 @@
|
|||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
|
00000002 # S mode write to menvcfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from menvcfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
|
00000002 # S mode write to mseccfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000002 # S mode read from mseccfg with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000bad
|
||||||
|
00000000
|
||||||
00000002 # U mode write to pmpcfg0 with illegal instruction
|
00000002 # U mode write to pmpcfg0 with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000002 # U mode read from pmpcfg0 with illegal instruction
|
00000002 # U mode read from pmpcfg0 with illegal instruction
|
||||||
|
@ -14,5 +14,9 @@
|
|||||||
00000000
|
00000000
|
||||||
00000011 # confirm read-only permissions of mhartid
|
00000011 # confirm read-only permissions of mhartid
|
||||||
00000000
|
00000000
|
||||||
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
|
00000000
|
||||||
|
00000011 # confirm read-only permissions of mconfigptr
|
||||||
|
00000000
|
||||||
0000000b # ecall from terminating tests in M mode
|
0000000b # ecall from terminating tests in M mode
|
||||||
00000000
|
00000000
|
||||||
|
@ -1,258 +0,0 @@
|
|||||||
///////////////////////////////////////////
|
|
||||||
// WALLY-AMO.S
|
|
||||||
//
|
|
||||||
// Tests Atomic AMO instructions
|
|
||||||
//
|
|
||||||
// David_Harris@hmc.edu 10 March 2021
|
|
||||||
//
|
|
||||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
// Adapted from Imperas RISCV-TEST_SUITE
|
|
||||||
//
|
|
||||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
|
||||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
|
||||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
|
||||||
// is furnished to do so, subject to the following conditions:
|
|
||||||
//
|
|
||||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
|
||||||
//
|
|
||||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
||||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
|
||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
///////////////////////////////////////////
|
|
||||||
|
|
||||||
#include "model_test.h"
|
|
||||||
#include "arch_test.h"
|
|
||||||
|
|
||||||
RVTEST_ISA("RV64IAF")
|
|
||||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo)
|
|
||||||
|
|
||||||
.section .text.init
|
|
||||||
.globl rvtest_entry_point
|
|
||||||
rvtest_entry_point:
|
|
||||||
RVMODEL_BOOT
|
|
||||||
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
# Addresses for test data and results
|
|
||||||
la x6, wally_signature
|
|
||||||
la x31, test_data
|
|
||||||
|
|
||||||
# Testcase 0: amoswap.w
|
|
||||||
li x7, 1
|
|
||||||
amoswap.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffffe (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 0000000000000001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 1: amoadd.w
|
|
||||||
li x7, 2
|
|
||||||
amoadd.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffffb (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be fffffffffffffffd (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 2: amoand.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amoand.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffffef (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ef (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 3: amoor.w
|
|
||||||
li x7, 0x44
|
|
||||||
amoor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffffbf (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 4: amoxor.w
|
|
||||||
li x7, 0x381
|
|
||||||
amoxor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be fffffffffffffd7e (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 5: amomax.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amomax.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 6: amomin.w
|
|
||||||
li x7, 0x7fd
|
|
||||||
amomin.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 7: amomaxu.w
|
|
||||||
li x7, 0x7fb
|
|
||||||
amomaxu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 8: amominu.w
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffeffff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
|
|
||||||
# Testcase 9: amoswap.d
|
|
||||||
li x7, 1
|
|
||||||
amoswap.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xfff7fffffffbffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0000000000000001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 10: amoadd.d
|
|
||||||
li x7, 2
|
|
||||||
amoadd.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xffdfffffffefffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xffdffffffff00001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 11: amoand.d
|
|
||||||
li x7, 0x7cf
|
|
||||||
amoand.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xff7fffffffbfffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007cf (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 12: amoor.d
|
|
||||||
li x7, 0x0d000011
|
|
||||||
amoor.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xfdfffffffeffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xfdffffffffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 13: amoxor.d
|
|
||||||
li x7, 0x381
|
|
||||||
amoxor.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xf7fffffffeffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xf7fffffffefffc7e (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 14: amomax.d
|
|
||||||
li x7, 0x7ff
|
|
||||||
amomax.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xdfffffffefffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 15: amomin.d
|
|
||||||
li x7, 0x7fd
|
|
||||||
amomin.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x7fffffffefffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fd (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 16: amomaxu.d
|
|
||||||
li x7, 0x7fb
|
|
||||||
amomaxu.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x00000001ffffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0x00000001ffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 17: amominu.d
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x0000000400000002 (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
RVMODEL_HALT
|
|
||||||
|
|
||||||
RVTEST_DATA_BEGIN
|
|
||||||
.align 8
|
|
||||||
test_data:
|
|
||||||
.dword 0xfffffffdfffffffe
|
|
||||||
.dword 0xfffffff7fffffffb
|
|
||||||
.dword 0xffffffdfffffffef
|
|
||||||
.dword 0xffffff7fffffffbf
|
|
||||||
.dword 0xfffffdfffffffeff
|
|
||||||
.dword 0xfffff7fffffffeff
|
|
||||||
.dword 0x0fffdfffffffefff
|
|
||||||
.dword 0xffff7fffffffefff
|
|
||||||
.dword 0x3ffdfffffffeffff
|
|
||||||
.dword 0xfff7fffffffbffff
|
|
||||||
.dword 0xffdfffffffefffff
|
|
||||||
.dword 0xff7fffffffbfffff
|
|
||||||
.dword 0xfdfffffffeffffff
|
|
||||||
.dword 0xf7fffffffeffffff
|
|
||||||
.dword 0xdfffffffefffffff
|
|
||||||
.dword 0x7fffffffefffffff
|
|
||||||
.dword 0x00000001ffffffff
|
|
||||||
.dword 0x0000000400000002
|
|
||||||
.dword 0x0000001000000008
|
|
||||||
.dword 0x0000004000000020
|
|
||||||
.dword 0x0000010000000080
|
|
||||||
.dword 0x0000040000000200
|
|
||||||
.dword 0x0000100000000800
|
|
||||||
.dword 0x0000400000002000
|
|
||||||
.dword 0x0000000100008000
|
|
||||||
.dword 0x0004000000000002
|
|
||||||
.dword 0x0000001000080000
|
|
||||||
.dword 0x0040000000000020
|
|
||||||
.dword 0x0000010000800000
|
|
||||||
.dword 0x0400000000000200
|
|
||||||
.dword 0x0000100008000000
|
|
||||||
.dword 0x4000000000002000
|
|
||||||
.dword 0x0000000080000000
|
|
||||||
RVTEST_DATA_END
|
|
||||||
|
|
||||||
RVMODEL_DATA_BEGIN
|
|
||||||
# signature output
|
|
||||||
wally_signature:
|
|
||||||
.fill 36, 8, -1
|
|
||||||
|
|
||||||
#ifdef rvtest_mtrap_routine
|
|
||||||
#mtrap_sigptr:
|
|
||||||
# .fill 64*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef rvtest_gpr_save
|
|
||||||
#gpr_save:
|
|
||||||
# .fill 32*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
RVMODEL_DATA_END
|
|
@ -45,7 +45,7 @@ WRITE_READ_CSR mvendorid, 0x111
|
|||||||
WRITE_READ_CSR marchid, 0x111
|
WRITE_READ_CSR marchid, 0x111
|
||||||
WRITE_READ_CSR mimpid, 0x111
|
WRITE_READ_CSR mimpid, 0x111
|
||||||
WRITE_READ_CSR mhartid, 0x111
|
WRITE_READ_CSR mhartid, 0x111
|
||||||
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||||
|
|
||||||
# Machine Trap Setup
|
# Machine Trap Setup
|
||||||
WRITE_READ_CSR mstatus, 0x111
|
WRITE_READ_CSR mstatus, 0x111
|
||||||
@ -62,12 +62,10 @@ WRITE_READ_CSR mepc, 0x111
|
|||||||
WRITE_READ_CSR mcause, 0x111
|
WRITE_READ_CSR mcause, 0x111
|
||||||
WRITE_READ_CSR mtval, 0x111
|
WRITE_READ_CSR mtval, 0x111
|
||||||
WRITE_READ_CSR mip, 0x111
|
WRITE_READ_CSR mip, 0x111
|
||||||
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
|
|
||||||
# WRITE_READ_CSR mtval2, 0x111
|
|
||||||
|
|
||||||
# Machine Configuration
|
# Machine Configuration
|
||||||
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
|
WRITE_READ_CSR menvcfg, 0x111
|
||||||
# WRITE_READ_CSR mseccgf, 0x111
|
WRITE_READ_CSR mseccfg, 0x111
|
||||||
|
|
||||||
# Machine Memory Protection
|
# Machine Memory Protection
|
||||||
WRITE_READ_CSR pmpcfg0, 0x111
|
WRITE_READ_CSR pmpcfg0, 0x111
|
||||||
|
@ -61,7 +61,7 @@ WRITE_READ_CSR mvendorid, 0x111
|
|||||||
WRITE_READ_CSR marchid, 0x111
|
WRITE_READ_CSR marchid, 0x111
|
||||||
WRITE_READ_CSR mimpid, 0x111
|
WRITE_READ_CSR mimpid, 0x111
|
||||||
WRITE_READ_CSR mhartid, 0x111
|
WRITE_READ_CSR mhartid, 0x111
|
||||||
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||||
|
|
||||||
# Machine Trap Setup
|
# Machine Trap Setup
|
||||||
WRITE_READ_CSR mstatus, 0x111
|
WRITE_READ_CSR mstatus, 0x111
|
||||||
@ -78,12 +78,10 @@ WRITE_READ_CSR mepc, 0x111
|
|||||||
WRITE_READ_CSR mcause, 0x111
|
WRITE_READ_CSR mcause, 0x111
|
||||||
WRITE_READ_CSR mtval, 0x111
|
WRITE_READ_CSR mtval, 0x111
|
||||||
WRITE_READ_CSR mip, 0x111
|
WRITE_READ_CSR mip, 0x111
|
||||||
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
|
|
||||||
# WRITE_READ_CSR mtval2, 0x111
|
|
||||||
|
|
||||||
# Machine Configuration
|
# Machine Configuration
|
||||||
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
|
WRITE_READ_CSR menvcfg, 0x111
|
||||||
# WRITE_READ_CSR mseccgf, 0x111
|
WRITE_READ_CSR mseccfg, 0x111
|
||||||
|
|
||||||
# Machine Memory Protection
|
# Machine Memory Protection
|
||||||
WRITE_READ_CSR pmpcfg0, 0x111
|
WRITE_READ_CSR pmpcfg0, 0x111
|
||||||
|
@ -23,7 +23,7 @@
|
|||||||
|
|
||||||
#include "WALLY-TEST-LIB-64.h"
|
#include "WALLY-TEST-LIB-64.h"
|
||||||
RVTEST_ISA("RV64I_Zicsr")
|
RVTEST_ISA("RV64I_Zicsr")
|
||||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
|
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo)
|
||||||
|
|
||||||
INIT_TESTS
|
INIT_TESTS
|
||||||
|
|
||||||
@ -34,7 +34,7 @@ CSR_R_ACCESS mvendorid
|
|||||||
CSR_R_ACCESS marchid
|
CSR_R_ACCESS marchid
|
||||||
CSR_R_ACCESS mimpid
|
CSR_R_ACCESS mimpid
|
||||||
CSR_R_ACCESS mhartid
|
CSR_R_ACCESS mhartid
|
||||||
# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
|
CSR_R_ACCESS mconfigptr
|
||||||
|
|
||||||
END_TESTS
|
END_TESTS
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user