Merge pull request #363 from ross144/main

Fixed over logging issue with icache and dcache loggers.

linux/devicetree/wally-artya7.dts

@@ -0,0 +1,76 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "wally-virt";
+	model = "wally-virt,qemu";
+
+	chosen {
+		linux,initrd-end = <0x85c43a00>;
+		linux,initrd-start = <0x84200000>;
+		bootargs = "root=/dev/vda ro";
+		stdout-path = "/soc/uart@10000000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x00 0x08000000>;
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		clock-frequency = <0xE4E1C0>;
+		timebase-frequency = <0xE4E1C0>;
+
+		cpu@0 {
+			phandle = <0x01>;
+			device_type = "cpu";
+			reg = <0x00>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcsu";
+			mmu-type = "riscv,sv48";
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x02>;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart@10000000 {
+			interrupts = <0x0a>;
+			interrupt-parent = <0x03>;
+			clock-frequency = <0xE4E1C0>;
+			reg = <0x00 0x10000000 0x00 0x100>;
+			compatible = "ns16550a";
+		};
+
+		plic@c000000 {
+			phandle = <0x03>;
+			riscv,ndev = <0x35>;
+			reg = <0x00 0xc000000 0x00 0x210000>;
+			interrupts-extended = <0x02 0x0b 0x02 0x09>;
+			interrupt-controller;
+			compatible = "sifive,plic-1.0.0\0riscv,plic0";
+			#interrupt-cells = <0x01>;
+			#address-cells = <0x00>;
+		};
+
+		clint@2000000 {
+			interrupts-extended = <0x02 0x03 0x02 0x07>;
+			reg = <0x00 0x2000000 0x00 0x10000>;
+			compatible = "sifive,clint0\0riscv,clint0";
+		};
+	};
+};

sim/wally.xrun

@@ -1,2 +1,6 @@
-xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
+xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
-xrun -elaborate -top testbench ../testbench/testbench.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench
+xrun -elaborate -top testbench ../testbench/testbench-xcelium.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench
+
+
+xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -top testbench -defparam testbench.TEST=arch64i
+

src/cache/cachefsm.sv

@@ -92,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;
 
   // outputs for the performance counters.
-  assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
+  assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
+                                     (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
   assign CacheMiss = CacheAccess & ~CacheHit;
 
   // special case on reset. When the fsm first exists reset the

src/privileged/csrc.sv

@@ -101,10 +101,10 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
     assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
     assign CounterEvent[12] = StoreStallM;                                               //  Store Stall
-    assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM;                      // data cache access
+    assign CounterEvent[13] = DCacheAccess;                                              // data cache access
     assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[15] = DCacheStallM;                                              // d cache miss cycles
-    assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM;                      // instruction cache access
+    assign CounterEvent[16] = ICacheAccess;                                              // instruction cache access
     assign CounterEvent[17] = ICacheMiss;                                                // instruction cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[18] = ICacheStallF;                                              // i cache miss cycles
     assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                         // CSR writes

testbench/common/loggers.sv

@@ -138,6 +138,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
     assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
                     dut.core.ifu.immu.immu.pmachecker.Cacheable &
                     ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
+                    dut.core.ifu.bus.icache.icache.cachefsm.CacheEn &
                     ~reset;
     flop #(1) ResetDReg(clk, reset, resetD);
     assign resetEdge = ~reset & resetD;
@@ -190,6 +191,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
     assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
                      ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
                      dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
+                     dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &
                      (AccessTypeString != "NULL");
 
     initial begin

testbench/common/wallyTracer.sv

@@ -61,6 +61,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [`NUM_CSRS-1:0] 		 CSR_W;
   logic 						 CSRWriteM, CSRWriteW;
   logic [11:0] 					 CSRAdrM, CSRAdrW;
+  logic                          wfiM;
+  logic                          InterruptM;
     
   assign clk = testbench.dut.clk;
   //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
@@ -88,6 +90,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
   assign STATUS_SXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
   assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
+  assign wfiM           = testbench.dut.core.priv.priv.wfiM;
+  assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
+  
 
   logic valid;
   int csrid;