mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Towards allowing dtim + bus.
This commit is contained in:
parent
81a2fbb6d2
commit
3dbf6790e1
3
pipelined/src/cache/cache.sv
vendored
3
pipelined/src/cache/cache.sv
vendored
@ -144,12 +144,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
|||||||
mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal);
|
mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal);
|
||||||
end else assign HitWayFinal = HitWay;
|
end else assign HitWayFinal = HitWay;
|
||||||
|
|
||||||
|
|
||||||
// like to fix this.
|
// like to fix this.
|
||||||
if(DCACHE)
|
if(DCACHE)
|
||||||
mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
|
mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
|
||||||
.d1(WordCount), .s(LSUBusWriteCrit),
|
.d1(WordCount), .s(LSUBusWriteCrit),
|
||||||
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
|
.y(WordOffsetAddr));
|
||||||
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
|
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
|
||||||
|
|
||||||
subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread(
|
subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread(
|
||||||
|
5
pipelined/src/cache/subcachelineread.sv
vendored
5
pipelined/src/cache/subcachelineread.sv
vendored
@ -39,11 +39,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)(
|
|||||||
output logic [WORDLEN-1:0] ReadDataWord);
|
output logic [WORDLEN-1:0] ReadDataWord);
|
||||||
|
|
||||||
localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
|
localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
|
||||||
|
// pad is for icache. Muxing extends over the cacheline boundary.
|
||||||
localparam PADLEN = WORDLEN-MUXINTERVAL;
|
localparam PADLEN = WORDLEN-MUXINTERVAL;
|
||||||
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
|
|
||||||
// easily build a variable input mux.
|
|
||||||
// *** move this to LSU and IFU, also remove mux from busdp into LSU.
|
|
||||||
// *** give this a module name to match block diagram
|
|
||||||
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
||||||
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
||||||
logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
|
logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
|
||||||
|
@ -177,7 +177,7 @@ module ifu (
|
|||||||
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
|
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
|
||||||
.TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
|
.TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
|
||||||
.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
|
.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
|
||||||
.BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF),
|
.BusCommittedM(), .DCacheStallM(ICacheStallF),
|
||||||
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
|
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
|
||||||
|
|
||||||
end else begin : bus
|
end else begin : bus
|
||||||
|
@ -43,7 +43,6 @@ module dtim(
|
|||||||
output logic LSUBusWrite,
|
output logic LSUBusWrite,
|
||||||
output logic LSUBusRead,
|
output logic LSUBusRead,
|
||||||
output logic BusCommittedM,
|
output logic BusCommittedM,
|
||||||
output logic [`XLEN-1:0] ReadDataWordMuxM,
|
|
||||||
output logic DCacheStallM,
|
output logic DCacheStallM,
|
||||||
output logic DCacheCommittedM,
|
output logic DCacheCommittedM,
|
||||||
output logic DCacheMiss,
|
output logic DCacheMiss,
|
||||||
@ -58,7 +57,6 @@ module dtim(
|
|||||||
// since we have a local memory the bus connections are all disabled.
|
// since we have a local memory the bus connections are all disabled.
|
||||||
// There are no peripherals supported.
|
// There are no peripherals supported.
|
||||||
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
|
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
|
||||||
assign ReadDataWordMuxM = ReadDataWordM;
|
|
||||||
assign {DCacheStallM, DCacheCommittedM} = '0;
|
assign {DCacheStallM, DCacheCommittedM} = '0;
|
||||||
assign {DCacheMiss, DCacheAccess} = '0;
|
assign {DCacheMiss, DCacheAccess} = '0;
|
||||||
|
|
||||||
|
@ -194,9 +194,10 @@ module lsu (
|
|||||||
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
|
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
|
||||||
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
|
dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM,
|
||||||
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
|
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
|
||||||
.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM,
|
.DCacheStallM, .DCacheCommittedM, .ByteMaskM,
|
||||||
.DCacheMiss, .DCacheAccess);
|
.DCacheMiss, .DCacheAccess);
|
||||||
assign SelUncachedAdr = '0; // value does not matter.
|
assign SelUncachedAdr = '0; // value does not matter.
|
||||||
|
assign ReadDataWordMuxM = ReadDataWordM;
|
||||||
end else begin : bus
|
end else begin : bus
|
||||||
localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1;
|
localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1;
|
||||||
localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;
|
localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;
|
||||||
|
Loading…
Reference in New Issue
Block a user