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Removed unused StallW from CSRs

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This commit is contained in:
David Harris 2022-12-23 00:21:36 -08:00
parent 9e21358d75
commit 3b1fe78bdc
5 changed files with 8 additions and 8 deletions
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8
pipelined/src/privileged/csr.sv
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@ -199,7 +199,7 @@ module csr #(parameter
// CSRs // CSRs
/////////////////////////////////////////// ///////////////////////////////////////////
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, csri csri(.clk, .reset, .InstrValidNotFlushedM,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
@ -219,7 +219,7 @@ module csr #(parameter
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
csrm csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW, csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
.CSRMWriteM, .MTrapM, .CSRAdrM, .CSRMWriteM, .MTrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW, .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW, .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
@ -227,7 +227,7 @@ module csr #(parameter
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM); .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
csrs csrs(.clk, .reset, .InstrValidNotFlushedM, .StallW, csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
.CSRSWriteM, .STrapM, .CSRAdrM, .CSRSWriteM, .STrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
@ -235,7 +235,7 @@ module csr #(parameter
.SCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.WriteSSTATUSM, .IllegalCSRSAccessM); .WriteSSTATUSM, .IllegalCSRSAccessM);
csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, csru csru(.clk, .reset, .InstrValidNotFlushedM,
.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
.IllegalCSRUAccessM); .IllegalCSRUAccessM);

2
pipelined/src/privileged/csri.sv
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@ -38,7 +38,7 @@ module csri #(parameter
SIP = 12'h144 SIP = 12'h144
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic InstrValidNotFlushedM, StallW, input logic InstrValidNotFlushedM,
input logic CSRMWriteM, CSRSWriteM, input logic CSRMWriteM, CSRSWriteM,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,

2
pipelined/src/privileged/csrm.sv
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@ -72,7 +72,7 @@ module csrm #(parameter
MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic InstrValidNotFlushedM, StallW, input logic InstrValidNotFlushedM,
input logic CSRMWriteM, MTrapM, input logic CSRMWriteM, MTrapM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,

2
pipelined/src/privileged/csrs.sv
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@ -50,7 +50,7 @@ module csrs #(parameter
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic InstrValidNotFlushedM, StallW, input logic InstrValidNotFlushedM,
input logic CSRSWriteM, STrapM, input logic CSRSWriteM, STrapM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,

2
pipelined/src/privileged/csru.sv
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@ -37,7 +37,7 @@ module csru #(parameter
FRM = 12'h002, FRM = 12'h002,
FCSR = 12'h003) ( FCSR = 12'h003) (
input logic clk, reset, input logic clk, reset,
input logic InstrValidNotFlushedM, StallW, input logic InstrValidNotFlushedM,
input logic CSRUWriteM, input logic CSRUWriteM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,