From 3b1fe78bdcea554b9b3c69e2ddd1b91a1ef5fcfa Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 23 Dec 2022 00:21:36 -0800
Subject: [PATCH] Removed unused StallW from CSRs

---
 pipelined/src/privileged/csr.sv  | 8 ++++----
 pipelined/src/privileged/csri.sv | 2 +-
 pipelined/src/privileged/csrm.sv | 2 +-
 pipelined/src/privileged/csrs.sv | 2 +-
 pipelined/src/privileged/csru.sv | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index dbb852e84..0932bcc74 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -199,7 +199,7 @@ module csr #(parameter
   // CSRs
   ///////////////////////////////////////////
 
-  csri   csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, 
+  csri   csri(.clk, .reset, .InstrValidNotFlushedM,  
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
               .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
@@ -219,7 +219,7 @@ module csr #(parameter
               .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
               .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
               .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
-  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW,
+  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM, 
               .CSRMWriteM, .MTrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
               .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
@@ -227,7 +227,7 @@ module csr #(parameter
               .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
               .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
               .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
-  csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM, .StallW,
+  csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM,
               .CSRSWriteM, .STrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
               .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
@@ -235,7 +235,7 @@ module csr #(parameter
               .SCOUNTEREN_REGW,
               .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
               .WriteSSTATUSM, .IllegalCSRSAccessM);
-  csru  csru(.clk, .reset, .InstrValidNotFlushedM, .StallW,
+  csru  csru(.clk, .reset, .InstrValidNotFlushedM, 
               .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
               .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
               .IllegalCSRUAccessM);
diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv
index aa4de62af..21102afdb 100644
--- a/pipelined/src/privileged/csri.sv
+++ b/pipelined/src/privileged/csri.sv
@@ -38,7 +38,7 @@ module csri #(parameter
     SIP = 12'h144
   ) (
     input logic 			clk, reset, 
-    input logic 			InstrValidNotFlushedM, StallW,
+    input logic 			InstrValidNotFlushedM,
     input logic 			CSRMWriteM, CSRSWriteM,
     input logic [`XLEN-1:0] CSRWriteValM,
     input logic [11:0] 		CSRAdrM,
diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv
index 3a8e73ee6..71368d065 100644
--- a/pipelined/src/privileged/csrm.sv
+++ b/pipelined/src/privileged/csrm.sv
@@ -72,7 +72,7 @@ module csrm #(parameter
     MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
   ) (
     input logic 	     clk, reset, 
-    input logic 	     InstrValidNotFlushedM, StallW,
+    input logic 	     InstrValidNotFlushedM, 
     input logic 	     CSRMWriteM, MTrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv
index 7d3aeeb94..b43067387 100644
--- a/pipelined/src/privileged/csrs.sv
+++ b/pipelined/src/privileged/csrs.sv
@@ -50,7 +50,7 @@ module csrs #(parameter
 
   ) (
     input logic 	     clk, reset, 
-    input logic 	     InstrValidNotFlushedM, StallW,
+    input logic 	     InstrValidNotFlushedM, 
     input logic 	     CSRSWriteM, STrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, 
diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv
index 7d1c5cbe5..c1eea42c3 100644
--- a/pipelined/src/privileged/csru.sv
+++ b/pipelined/src/privileged/csru.sv
@@ -37,7 +37,7 @@ module csru #(parameter
   FRM = 12'h002,
   FCSR = 12'h003) (
     input  logic             clk, reset, 
-    input  logic             InstrValidNotFlushedM, StallW,
+    input  logic             InstrValidNotFlushedM,
     input  logic             CSRUWriteM,
     input  logic [11:0]      CSRAdrM,
     input  logic [`XLEN-1:0] CSRWriteValM,