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update removal of underscores from sha_instructions

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This commit is contained in:
James E. Stine 2024-03-09 18:51:01 -06:00
parent 08c7ddd61d
commit 3b16238a37
6 changed files with 24 additions and 24 deletions
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4
src/ieu/sha_instructions/sha512sig0h.sv
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@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// RS1 Shifts // RS1 Shifts
logic [31:0] shift1; logic [31:0] shift1;
@ -47,6 +47,6 @@ module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2,
assign shift24 = rs2 << 24; assign shift24 = rs2 << 24;
// XOR to get result // XOR to get result
assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24; assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
endmodule endmodule

4
src/ieu/sha_instructions/sha512sig0l.sv
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@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// rs1 operations // rs1 operations
logic [31:0] shift1; logic [31:0] shift1;
@ -48,6 +48,6 @@ module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2,
assign shift25 = rs2 << 25; assign shift25 = rs2 << 25;
assign shift24 = rs2 << 24; assign shift24 = rs2 << 24;
assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24; assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
endmodule endmodule

4
src/ieu/sha_instructions/sha512sig1h.sv
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@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// rs1 shifts // rs1 shifts
logic [31:0] shift3; logic [31:0] shift3;
@ -45,7 +45,7 @@ module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2,
assign shift13 = rs2 << 13; assign shift13 = rs2 << 13;
// XOR Shifted registers for output // XOR Shifted registers for output
assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13; assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
endmodule endmodule

4
src/ieu/sha_instructions/sha512sig1l.sv
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@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// rs1 shift logic // rs1 shift logic
logic [31:0] shift3; logic [31:0] shift3;
@ -48,6 +48,6 @@ module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2,
assign shift26 = rs2 << 26; assign shift26 = rs2 << 26;
assign shift13 = rs2 << 13; assign shift13 = rs2 << 13;
assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13; assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
endmodule endmodule

4
src/ieu/sha_instructions/sha512sum0r.sv
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@ -26,7 +26,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// RS1 shifts // RS1 shifts
logic [31:0] shift25; logic [31:0] shift25;
@ -49,6 +49,6 @@ module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2,
assign shift4 = rs2 << 4; assign shift4 = rs2 << 4;
// Set output to XOR of shifted values // Set output to XOR of shifted values
assign data_out = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4; assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
endmodule endmodule

28
src/ieu/sha_instructions/sha512sum1r.sv
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@ -26,29 +26,29 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1r(input logic [31:0] rs1, input logic [31:0] rs2, module sha512sum1r(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] data_out); output logic [31:0] DataOut);
// Declare logic for rs1 shifts // Declare logic for rs1 shifts
logic [31:0] shift1_23; logic [31:0] shift1by23;
logic [31:0] shift1_14; logic [31:0] shift1by14;
logic [31:0] shift1_18; logic [31:0] shift1by18;
// Declare logic for rs2 shifts // Declare logic for rs2 shifts
logic [31:0] shift2_9; logic [31:0] shift2by9;
logic [31:0] shift2_18; logic [31:0] shift2by18;
logic [31:0] shift2_14; logic [31:0] shift2by14;
// Shift RS1 // Shift RS1
assign shift1_23 = rs1 << 23; assign shift1by23 = rs1 << 23;
assign shift1_14 = rs1 >> 14; assign shift1by14 = rs1 >> 14;
assign shift1_18 = rs1 >> 18; assign shift1by18 = rs1 >> 18;
// Shift RS2 // Shift RS2
assign shift2_9 = rs2 >> 9; assign shift2by9 = rs2 >> 9;
assign shift2_18 = rs2 << 18; assign shift2by18 = rs2 << 18;
assign shift2_14 = rs2 << 14; assign shift2by14 = rs2 << 14;
// Assign output to xor of shifts // Assign output to xor of shifts
assign data_out = shift1_23 ^ shift1_14 ^ shift1_18 ^ shift2_9 ^ shift2_18 ^ shift2_14; assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14;
endmodule endmodule