diff --git a/src/ieu/sha_instructions/sha512sig0h.sv b/src/ieu/sha_instructions/sha512sig0h.sv
index a26ae0ef7..8074dc9a3 100644
--- a/src/ieu/sha_instructions/sha512sig0h.sv
+++ b/src/ieu/sha_instructions/sha512sig0h.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sig0h(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);
+                   output logic [31:0] DataOut);
    
    // RS1 Shifts
    logic [31:0] 		       shift1;
@@ -47,6 +47,6 @@ module sha512sig0h(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift24 = rs2 << 24;
    
    // XOR to get result
-   assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
+   assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
     
 endmodule
diff --git a/src/ieu/sha_instructions/sha512sig0l.sv b/src/ieu/sha_instructions/sha512sig0l.sv
index a12568fb5..0f0df38e9 100644
--- a/src/ieu/sha_instructions/sha512sig0l.sv
+++ b/src/ieu/sha_instructions/sha512sig0l.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sig0l(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);
+                   output logic [31:0] DataOut);
    
    // rs1 operations                   
    logic [31:0] 		       shift1;
@@ -48,6 +48,6 @@ module sha512sig0l(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift25 = rs2 << 25;
    assign shift24 = rs2 << 24;
    
-   assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
+   assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
    
 endmodule
diff --git a/src/ieu/sha_instructions/sha512sig1h.sv b/src/ieu/sha_instructions/sha512sig1h.sv
index cce4b593b..7929852d0 100644
--- a/src/ieu/sha_instructions/sha512sig1h.sv
+++ b/src/ieu/sha_instructions/sha512sig1h.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sig1h(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);
+                   output logic [31:0] DataOut);
    
    // rs1 shifts             
    logic [31:0] 		       shift3;
@@ -45,7 +45,7 @@ module sha512sig1h(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift13 = rs2 << 13;
    
    // XOR Shifted registers for output
-   assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
+   assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
     
 endmodule
     
diff --git a/src/ieu/sha_instructions/sha512sig1l.sv b/src/ieu/sha_instructions/sha512sig1l.sv
index dae623091..f8ba1d9f4 100644
--- a/src/ieu/sha_instructions/sha512sig1l.sv
+++ b/src/ieu/sha_instructions/sha512sig1l.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sig1l(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);
+                   output logic [31:0] DataOut);
                   
    // rs1 shift logic
    logic [31:0] 		       shift3;
@@ -48,6 +48,6 @@ module sha512sig1l(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift26 = rs2 << 26;
    assign shift13 = rs2 << 13;
    
-   assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
+   assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
                             
 endmodule
diff --git a/src/ieu/sha_instructions/sha512sum0r.sv b/src/ieu/sha_instructions/sha512sum0r.sv
index e7ccf4e6e..1f92e6fdc 100644
--- a/src/ieu/sha_instructions/sha512sum0r.sv
+++ b/src/ieu/sha_instructions/sha512sum0r.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sum0r(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);
+                   output logic [31:0] DataOut);
    
    // RS1 shifts
    logic [31:0] 		       shift25;
@@ -49,6 +49,6 @@ module sha512sum0r(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift4 = rs2 << 4;
    
    // Set output to XOR of shifted values
-   assign data_out = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
+   assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
    
 endmodule
diff --git a/src/ieu/sha_instructions/sha512sum1r.sv b/src/ieu/sha_instructions/sha512sum1r.sv
index 36ccbc1be..0cf46e82c 100644
--- a/src/ieu/sha_instructions/sha512sum1r.sv
+++ b/src/ieu/sha_instructions/sha512sum1r.sv
@@ -26,29 +26,29 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module sha512sum1r(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] data_out);   
+                   output logic [31:0] DataOut);   
    
    // Declare logic for rs1 shifts
-   logic [31:0] 		       shift1_23;
-   logic [31:0] 		       shift1_14;
-   logic [31:0] 		       shift1_18;
+   logic [31:0] 		       shift1by23;
+   logic [31:0] 		       shift1by14;
+   logic [31:0] 		       shift1by18;
    
    // Declare logic for rs2 shifts
-   logic [31:0] 		       shift2_9;
-   logic [31:0] 		       shift2_18;
-   logic [31:0] 		       shift2_14;
+   logic [31:0] 		       shift2by9;
+   logic [31:0] 		       shift2by18;
+   logic [31:0] 		       shift2by14;
    
    // Shift RS1
-   assign shift1_23 = rs1 << 23;
-   assign shift1_14 = rs1 >> 14;
-   assign shift1_18 = rs1 >> 18;
+   assign shift1by23 = rs1 << 23;
+   assign shift1by14 = rs1 >> 14;
+   assign shift1by18 = rs1 >> 18;
    
    // Shift RS2
-   assign shift2_9 = rs2 >> 9;
-   assign shift2_18 = rs2 << 18;
-   assign shift2_14 = rs2 << 14;
+   assign shift2by9 = rs2 >> 9;
+   assign shift2by18 = rs2 << 18;
+   assign shift2by14 = rs2 << 14;
    
    // Assign output to xor of shifts
-   assign data_out = shift1_23 ^ shift1_14 ^ shift1_18 ^ shift2_9 ^ shift2_18 ^ shift2_14;
+   assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14;
     
 endmodule