From 3a2e8ae3ccc2d1367d86a13b4438e84728b937b6 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Sat, 15 Jun 2024 22:01:49 -0500
Subject: [PATCH] just in case: add rad.sv with comment + new cfg for openocd

---
 src/debug/rad.sv               | 5 ++++-
 tests/debug/simple/openocd.cfg | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/debug/rad.sv b/src/debug/rad.sv
index ede1effcb..29efc371c 100644
--- a/src/debug/rad.sv
+++ b/src/debug/rad.sv
@@ -110,7 +110,10 @@ module rad import cvw::*; #(parameter cvw_t P) (
       `MIP_REGNO : begin
         ShiftCount = P.LLEN - 1;
         CSRegNo = 1;
-        RegReadOnly = 1;
+	// Comment out because gives error on openocd
+	// This value cause the csrs to all go read-only
+	// which openocd doesnt like
+        //RegReadOnly = 1;
       end
 
       [`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
diff --git a/tests/debug/simple/openocd.cfg b/tests/debug/simple/openocd.cfg
index 6bc8d78d2..40a9ed4e5 100644
--- a/tests/debug/simple/openocd.cfg
+++ b/tests/debug/simple/openocd.cfg
@@ -22,7 +22,7 @@ adapter speed 1000
 #ftdi tdo_sample_edge falling
 
 set _CHIPNAME cvw
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002A005
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002AC05
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME