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renamed DivStart

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This commit is contained in:
David Harris 2021-10-10 08:32:04 -07:00
parent 64ed267825
commit 39bbeefa78
2 changed files with 8 additions and 8 deletions
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8
wally-pipelined/src/muldiv/intdivrestoring.sv
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@ -32,7 +32,7 @@ module intdivrestoring (
input logic reset, input logic reset,
input logic StallM, FlushM, input logic StallM, FlushM,
input logic DivSignedE, W64E, input logic DivSignedE, W64E,
input logic StartDivideE, input logic DivStartE,
input logic [`XLEN-1:0] SrcAE, SrcBE, input logic [`XLEN-1:0] SrcAE, SrcBE,
output logic BusyE, DivDoneM, output logic BusyE, DivDoneM,
output logic [`XLEN-1:0] QuotM, RemM output logic [`XLEN-1:0] QuotM, RemM
@ -50,8 +50,8 @@ module intdivrestoring (
// save inputs on the negative edge of the execute clock. // save inputs on the negative edge of the execute clock.
// This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic. // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
// Saving the inputs is the most hardware-efficient way to fix the issue. // Saving the inputs is the most hardware-efficient way to fix the issue.
flopen #(`XLEN) xsavereg(~clk, StartDivideE, SrcAE, XSavedE); flopen #(`XLEN) xsavereg(~clk, DivStartE, SrcAE, XSavedE);
flopen #(`XLEN) dsavereg(~clk, StartDivideE, SrcBE, DSavedE); flopen #(`XLEN) dsavereg(~clk, DivStartE, SrcBE, DSavedE);
// Handle sign extension for W-type instructions // Handle sign extension for W-type instructions
generate generate
@ -111,7 +111,7 @@ module intdivrestoring (
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) begin if (reset) begin
BusyE = 0; DivDoneM = 0; step = 0; DivInitE = 0; BusyE = 0; DivDoneM = 0; step = 0; DivInitE = 0;
end else if (StartDivideE & ~StallM) begin end else if (DivStartE & ~StallM) begin
if (Div0E) DivDoneM = 1; if (Div0E) DivDoneM = 1;
else begin else begin
BusyE = 1; step = 0; DivInitE = 1; BusyE = 1; step = 0; DivInitE = 1;

8
wally-pipelined/src/muldiv/muldiv.sv
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@ -48,7 +48,7 @@ module muldiv (
logic [`XLEN-1:0] QuotM, RemM; logic [`XLEN-1:0] QuotM, RemM;
logic [`XLEN*2-1:0] ProdE, ProdM; logic [`XLEN*2-1:0] ProdE, ProdM;
logic StartDivideE, BusyE, DivDoneM; logic DivStartE, BusyE, DivDoneM;
logic DivSignedE; logic DivSignedE;
logic W64M; logic W64M;
@ -58,11 +58,11 @@ module muldiv (
// Divide // Divide
// Start a divide when a new division instruction is received and the divider isn't already busy or finishing // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
assign StartDivideE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM; assign DivStartE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM;
assign DivBusyE = StartDivideE | BusyE; assign DivBusyE = DivStartE | BusyE;
assign DivSignedE = ~Funct3E[0]; assign DivSignedE = ~Funct3E[0];
intdivrestoring div(.clk, .reset, .StallM, .FlushM, intdivrestoring div(.clk, .reset, .StallM, .FlushM,
.DivSignedE, .W64E, .StartDivideE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM); .DivSignedE, .W64E, .DivStartE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
// Result multiplexer // Result multiplexer
always_comb always_comb