From 39bbeefa78532e31271d13b9aca63d300b00ea5a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 10 Oct 2021 08:32:04 -0700
Subject: [PATCH] renamed DivStart

---
 wally-pipelined/src/muldiv/intdivrestoring.sv | 8 ++++----
 wally-pipelined/src/muldiv/muldiv.sv          | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv
index 2a78ec0f6..9dd60f8d1 100644
--- a/wally-pipelined/src/muldiv/intdivrestoring.sv
+++ b/wally-pipelined/src/muldiv/intdivrestoring.sv
@@ -32,7 +32,7 @@ module intdivrestoring (
   input  logic reset,
   input  logic StallM, FlushM,
   input  logic DivSignedE, W64E,
-  input  logic StartDivideE,
+  input  logic DivStartE,
   input  logic [`XLEN-1:0] SrcAE, SrcBE,
   output logic BusyE, DivDoneM,
   output logic [`XLEN-1:0] QuotM, RemM
@@ -50,8 +50,8 @@ module intdivrestoring (
   // save inputs on the negative edge of the execute clock.  
   // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
   // Saving the inputs is the most hardware-efficient way to fix the issue.
-  flopen #(`XLEN) xsavereg(~clk, StartDivideE, SrcAE, XSavedE);
-  flopen #(`XLEN) dsavereg(~clk, StartDivideE, SrcBE, DSavedE); 
+  flopen #(`XLEN) xsavereg(~clk, DivStartE, SrcAE, XSavedE);
+  flopen #(`XLEN) dsavereg(~clk, DivStartE, SrcBE, DSavedE); 
 
   // Handle sign extension for W-type instructions
   generate
@@ -111,7 +111,7 @@ module intdivrestoring (
   always_ff @(posedge clk) 
     if (reset) begin
         BusyE = 0; DivDoneM = 0; step = 0; DivInitE = 0;
-    end else if (StartDivideE & ~StallM) begin 
+    end else if (DivStartE & ~StallM) begin 
         if (Div0E) DivDoneM = 1;
         else begin
             BusyE = 1; step = 0; DivInitE = 1;
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index 11fb4ff1f..c38a6ce0c 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -48,7 +48,7 @@ module muldiv (
 	 logic [`XLEN-1:0] QuotM, RemM;
 	 logic [`XLEN*2-1:0] ProdE, ProdM; 
 
-	 logic 		     StartDivideE, BusyE, DivDoneM;
+	 logic 		     DivStartE, BusyE, DivDoneM;
 	 logic 		     DivSignedE;	
 	 logic           W64M; 
 	 
@@ -58,11 +58,11 @@ module muldiv (
 
 	 // Divide
 	 // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
-	 assign StartDivideE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM; 
-	 assign DivBusyE = StartDivideE | BusyE;
+	 assign DivStartE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM; 
+	 assign DivBusyE = DivStartE | BusyE;
 	 assign DivSignedE = ~Funct3E[0];
 	 intdivrestoring div(.clk, .reset, .StallM, .FlushM, 
-	   .DivSignedE, .W64E, .StartDivideE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
+	   .DivSignedE, .W64E, .DivStartE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
 	 	 
 	 // Result multiplexer
 	 always_comb