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Fixed TransmitStart resetting SCK and delay counter while already counting

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naichewa 2024-11-08 11:05:38 -08:00
parent e59ca12cdc
commit 396a17623b
1 changed files with 3 additions and 4 deletions
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7
src/uncore/spi_controller.sv
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@ -109,7 +109,6 @@ module spi_controller (
logic DelayIsNext; logic DelayIsNext;
logic DelayState; logic DelayState;
// Convenient Delay Reg Names // Convenient Delay Reg Names
assign cssck = Delay0[7:0]; assign cssck = Delay0[7:0];
assign sckcs = Delay0[15:8]; assign sckcs = Delay0[15:8];
@ -153,7 +152,7 @@ module spi_controller (
DelayCounter <= 0; DelayCounter <= 0;
end else begin end else begin
// SCK logic for delay times // SCK logic for delay times
if (TransmitStart) begin if (TransmitStart & ~DelayState) begin
SCK <= 0; SCK <= 0;
end else if (SCLKenable) begin end else if (SCLKenable) begin
SCK <= ~SCK; SCK <= ~SCK;
@ -168,7 +167,7 @@ module spi_controller (
// SPICLK Logic // SPICLK Logic
if (TransmitStart) begin if (TransmitStart & ~DelayState) begin
SPICLK <= SckMode[1]; SPICLK <= SckMode[1];
end else if (SCLKenable) begin end else if (SCLKenable) begin
if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
@ -176,7 +175,7 @@ module spi_controller (
end end
// Reset divider // Reset divider
if (SCLKenable | TransmitStart | ResetSCLKenable) begin if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin
DivCounter <= 12'b0; DivCounter <= 12'b0;
end else begin end else begin
DivCounter <= DivCounter + 12'd1; DivCounter <= DivCounter + 12'd1;