From 396a17623b070efc276790a2a1faa20f07e528d0 Mon Sep 17 00:00:00 2001
From: naichewa <nwhyteaguayo@g.hmc.edu>
Date: Fri, 8 Nov 2024 11:05:38 -0800
Subject: [PATCH] Fixed TransmitStart resetting SCK and delay counter while
 already counting

---
 src/uncore/spi_controller.sv | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
index 939457954..dee3d3c99 100644
--- a/src/uncore/spi_controller.sv
+++ b/src/uncore/spi_controller.sv
@@ -109,7 +109,6 @@ module spi_controller (
 
   logic       DelayIsNext;
   logic       DelayState;       
-
   // Convenient Delay Reg Names
   assign cssck = Delay0[7:0];
   assign sckcs = Delay0[15:8];
@@ -153,7 +152,7 @@ module spi_controller (
       DelayCounter <= 0;
     end else begin
       // SCK logic for delay times  
-      if (TransmitStart) begin
+      if (TransmitStart & ~DelayState) begin
         SCK <= 0;
       end else if (SCLKenable) begin
         SCK <= ~SCK;
@@ -168,7 +167,7 @@ module spi_controller (
       
       // SPICLK Logic
       
-      if (TransmitStart) begin
+      if (TransmitStart & ~DelayState) begin
         SPICLK <= SckMode[1];
       end else if (SCLKenable) begin
         if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
@@ -176,7 +175,7 @@ module spi_controller (
       end
       
       // Reset divider 
-      if (SCLKenable | TransmitStart | ResetSCLKenable) begin
+      if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin
         DivCounter <= 12'b0;
       end else begin
         DivCounter <= DivCounter + 12'd1;