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rv32gc now also works with the alignment module. Still not tested with misligned access.

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This commit is contained in:
Rose Thompson 2023-10-30 15:30:09 -05:00
parent f7b00c7af9
commit 3824c3be8d
3 changed files with 5 additions and 5 deletions
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6
src/lsu/align.sv
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@ -87,10 +87,10 @@ module align import cvw::*; #(parameter cvw_t P) (
// 1) operation size
// 2) offset
// 3) access location within the cacheline
logic [P.DCACHE_LINELENINBITS/8-1:P.LLEN/8] WordOffsetM;
logic [P.LLEN/8-1:0] ByteOffsetM;
logic [$clog2(P.DCACHE_LINELENINBITS/8)-1:$clog2(LLENINBYTES)] WordOffsetM;
logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
logic HalfSpillM, WordSpillM;
assign {WordOffsetM, ByteOffsetM} = IEUAdrM[P.DCACHE_LINELENINBITS/8-1:0];
assign {WordOffsetM, ByteOffsetM} = IEUAdrM[$clog2(P.DCACHE_LINELENINBITS/8)-1:0];
assign HalfSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b01 & ByteOffsetM[0] != 1'b0;
assign WordSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b10 & ByteOffsetM[1:0] != 2'b00;
if(P.LLEN == 64) begin

2
src/lsu/lsu.sv
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@ -151,7 +151,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
if(MISALIGN_SUPPORT) begin : ziccslm_align
logic [P.LLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
.MemRWM, .CacheableM,
.DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM,

2
src/lsu/swbytemask.sv
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@ -33,7 +33,7 @@ module swbytemask #(parameter WORDLEN)(
output logic [WORDLEN/8-1:0] ByteMask
);
assign ByteMask = ((2**(2**Size))-1) << Adr;
assign ByteMask = ((2**(2**Size))-1) << Adr; // merge with align.
/* Equivalent to the following