diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 48cf2f035..18dd6b2ff 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -87,10 +87,10 @@ module align import cvw::*;  #(parameter cvw_t P) (
   // 1) operation size
   // 2) offset
   // 3) access location within the cacheline
-  logic [P.DCACHE_LINELENINBITS/8-1:P.LLEN/8] WordOffsetM;
-  logic [P.LLEN/8-1:0]                 ByteOffsetM;
+  logic [$clog2(P.DCACHE_LINELENINBITS/8)-1:$clog2(LLENINBYTES)] WordOffsetM;
+  logic [$clog2(LLENINBYTES)-1:0]                 ByteOffsetM;
   logic                                HalfSpillM, WordSpillM;
-  assign {WordOffsetM, ByteOffsetM} = IEUAdrM[P.DCACHE_LINELENINBITS/8-1:0];
+  assign {WordOffsetM, ByteOffsetM} = IEUAdrM[$clog2(P.DCACHE_LINELENINBITS/8)-1:0];
   assign HalfSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b01 & ByteOffsetM[0] != 1'b0;
   assign WordSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b10 & ByteOffsetM[1:0] != 2'b00;
   if(P.LLEN == 64) begin
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 5b9533504..6cb123be8 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -151,7 +151,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
   flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   if(MISALIGN_SUPPORT) begin : ziccslm_align
-    logic [P.LLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
+    logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
                      .MemRWM, .CacheableM,
                      .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM,
diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv
index ad20a4414..9313456f3 100644
--- a/src/lsu/swbytemask.sv
+++ b/src/lsu/swbytemask.sv
@@ -33,7 +33,7 @@ module swbytemask #(parameter WORDLEN)(
   output logic [WORDLEN/8-1:0]         ByteMask
 );
   
-  assign ByteMask = ((2**(2**Size))-1) << Adr;
+  assign ByteMask = ((2**(2**Size))-1) << Adr; // merge with align.
 
 /* Equivalent to the following