From 37c930bb2774eb5b20b33f01b02f989e7d80ea5f Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Thu, 15 Jun 2023 10:39:37 -0700 Subject: [PATCH] Update wallypipelinedsoc.sv Program clean up --- src/wally/wallypipelinedsoc.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 03974fe51..af8c18ed1 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -51,9 +51,9 @@ module wallypipelinedsoc import cvw::*; ( output logic HREADY, // I/O Interface input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOIN, // inputs from GPIO - output logic [31:0] GPIOOUT, // output values for GPIO - output logic [31:0] GPIOEN, // output enables for GPIO + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output input logic SDCCmdIn, // SDC Command input