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added 'd' suffix to muxes for data-critical synths

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This commit is contained in:
Madeleine Masser-Frye 2022-06-10 21:11:05 +00:00
parent 88285c684c
commit 374dfd1fc2
2 changed files with 4 additions and 4 deletions
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6
pipelined/src/ppa/ppa.sv
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@ -525,7 +525,7 @@ module ppa_decoder #(parameter WIDTH = 8) (
end end
endmodule endmodule
module ppa_mux2_1 #(parameter WIDTH = 1) ( module ppa_mux2d_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1, input logic [WIDTH-1:0] d0, d1,
input logic s, input logic s,
output logic [WIDTH-1:0] y); output logic [WIDTH-1:0] y);
@ -533,7 +533,7 @@ module ppa_mux2_1 #(parameter WIDTH = 1) (
assign y = s ? d1 : d0; assign y = s ? d1 : d0;
endmodule endmodule
module ppa_mux4_1 #(parameter WIDTH = 1) ( module ppa_mux4d_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1, d2, d3, input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s, input logic [1:0] s,
output logic [WIDTH-1:0] y); output logic [WIDTH-1:0] y);
@ -541,7 +541,7 @@ module ppa_mux4_1 #(parameter WIDTH = 1) (
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule endmodule
module ppa_mux8_1 #(parameter WIDTH = 1) ( module ppa_mux8d_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7, input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s, input logic [2:0] s,
output logic [WIDTH-1:0] y); output logic [WIDTH-1:0] y);

2
synthDC/scripts/synth.tcl
View File

@ -74,7 +74,7 @@ if { $saifpower == 1 } {
if {$drive != "INV"} { if {$drive != "INV"} {
set_false_path -from [get_ports reset] set_false_path -from [get_ports reset]
} }
if {(($::env(DESIGN) == "ppa_mux2_1") || ($::env(DESIGN) == "ppa_mux4_1") || ($::env(DESIGN) == "ppa_mux8_1"))} { if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} {
set_false_path -from {s} set_false_path -from {s}
} }