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3714b2bf4a
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
82 lines
4.2 KiB
Systemverilog
82 lines
4.2 KiB
Systemverilog
//////////////////////////////////////////
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// pmachecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and identifies attributes of
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// the memory region accessed.
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// Can report illegal accesses to the trap unit and cause a fault.
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module pmachecker import cvw::*; #(parameter cvw_t P) (
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input logic [P.PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] Size,
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input logic [3:0] CMOpM,
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input logic AtomicAccessM, // Atomic access
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input logic ExecuteAccessF, // Execute access
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input logic WriteAccessM, // Write access
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input logic ReadAccessM, // Read access
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input logic [1:0] PBMemoryType, // PBMT field of PTE during TLB hit, or 00 otherwise
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output logic Cacheable, Idempotent, AllowShift, SelTIM,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAmoAccessFaultM
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);
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logic PMAAccessFault;
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logic AccessRW, AccessRWXC, AccessRX;
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logic [11:0] SelRegions;
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logic AtomicAllowed;
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logic CacheableRegion, IdempotentRegion;
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// Determine what type of access is being made
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assign AccessRW = ReadAccessM | WriteAccessM;
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assign AccessRWXC = ReadAccessM | WriteAccessM | ExecuteAccessF | (|CMOpM);
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assign AccessRX = ReadAccessM | ExecuteAccessF;
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// Determine which region of physical memory (if any) is being accessed
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adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXC, Size, SelRegions);
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// Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
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assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable
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assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;
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assign AllowShift = SelRegions[1] | SelRegions[2] | SelRegions[3] | SelRegions[5] | SelRegions[6];
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// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
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// I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent
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assign IdempotentRegion = SelRegions[1] | SelRegions[2] | SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-idempotent
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assign Idempotent = (PBMemoryType == 2'b00) ? IdempotentRegion : (PBMemoryType == 2'b01);
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// Atomic operations are only allowed on RAM
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assign AtomicAllowed = SelRegions[1] | SelRegions[3] | SelRegions[5]; // exclusion-tag: unused-atomic
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// Check if tightly integrated memories are selected
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assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-tim
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// Detect access faults
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assign PMAAccessFault = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed;
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assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
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assign PMAStoreAmoAccessFaultM = (WriteAccessM | (|CMOpM)) & PMAAccessFault;
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endmodule
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