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Restructured rconlut for modularity

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This commit is contained in:
David Harris 2024-03-16 07:26:40 -07:00
parent fedd23a3c0
commit 35f1c1d971
2 changed files with 26 additions and 24 deletions
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8
src/ieu/aes/aes64ks1i.sv
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@ -34,19 +34,17 @@ module aes64ks1i(
); );
logic finalround; logic finalround;
logic [7:0] rcon8;
logic [31:0] rcon, rs1Rotate; logic [31:0] rcon, rs1Rotate;
rconlut128 rc(round, rcon8); // Get rcon value from lookup table rconlut32 rc(round, rcon); // Get rcon value from lookup table
assign rcon = {24'b0, rcon8}; // Zero-pad RCON
assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value fo ruse in tmp2 assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value fo ruse in tmp2
assign finalround = (round == 4'b1010); // round 10 is the last one assign finalround = (round == 4'b1010); // round 10 is the last one
assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round
// Share sbox with encryption in zknde64. This module just sends value to shared sbox and gets result back // Share sbox with encryption in zknde64. This module just sends value to shared sbox and gets result back
// send out value as SboxKIn, get back subsittuted result as Sbox0Out // send out value as SboxKIn, get back subsittuted result as Sbox0Out
assign result[31:0] = Sbox0Out ^ rcon; assign result[31:0] = Sbox0Out ^ rcon;
assign result[63:32] = Sbox0Out ^ rcon; assign result[63:32] = Sbox0Out ^ rcon;
endmodule endmodule

42
src/ieu/aes/rconlut128.sv → src/ieu/aes/rconlut32.sv
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// rconlut128.sv // rconlut32.sv
// //
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024 // Created: 20 February 2024
@ -25,24 +25,28 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module rconlut128( module rconlut32(
input logic [3:0] rd, input logic [3:0] rd,
output logic [7:0] rconOut output logic [31:0] rcon
); );
logic [7:0] rcon8;
always_comb always_comb
case(rd) case(rd)
4'h0 : rconOut = 8'h01; 4'h0 : rcon8 = 8'h01;
4'h1 : rconOut = 8'h02; 4'h1 : rcon8 = 8'h02;
4'h2 : rconOut = 8'h04; 4'h2 : rcon8 = 8'h04;
4'h3 : rconOut = 8'h08; 4'h3 : rcon8 = 8'h08;
4'h4 : rconOut = 8'h10; 4'h4 : rcon8 = 8'h10;
4'h5 : rconOut = 8'h20; 4'h5 : rcon8 = 8'h20;
4'h6 : rconOut = 8'h40; 4'h6 : rcon8 = 8'h40;
4'h7 : rconOut = 8'h80; 4'h7 : rcon8 = 8'h80;
4'h8 : rconOut = 8'h1b; 4'h8 : rcon8 = 8'h1b;
4'h9 : rconOut = 8'h36; 4'h9 : rcon8 = 8'h36;
4'hA : rconOut = 8'h00; 4'hA : rcon8 = 8'h00;
default : rconOut = 8'h00; default : rcon8 = 8'h00;
endcase endcase
assign rcon = {24'b0, rcon8};
endmodule endmodule