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https://github.com/openhwgroup/cvw
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Cleaned up rvvisynth.sv
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Rose Thompson
parent
efa99940c5
commit
35e69944fa
@ -69,132 +69,6 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
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logic [10+2*P.XLEN-1:0] Registers;
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logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs;
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// get signals from the core.
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if (`FPGA) begin
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/* -----\/----- EXCLUDED -----\/-----
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assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
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assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
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assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
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assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
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assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
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assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
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assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
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assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
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assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
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assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
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assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
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assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
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assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
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assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
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assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
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assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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-----/\----- EXCLUDED -----/\----- */
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end else begin // if (`FPGA)
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/* -----\/----- EXCLUDED -----\/-----
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assign StallE = dut.core.StallE;
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assign StallM = dut.core.StallM;
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assign StallW = dut.core.StallW;
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assign FlushE = dut.core.FlushE;
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assign FlushM = dut.core.FlushM;
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assign FlushW = dut.core.FlushW;
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assign InstrValidM = dut.core.ieu.InstrValidM;
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assign InstrRawD = dut.core.ifu.InstrRawD;
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assign PCM = dut.core.ifu.PCM;
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assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = dut.core.TrapM;
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assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = dut.core.ieu.dp.regf.a3;
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assign GPRWen = dut.core.ieu.dp.regf.we3;
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assign GPRValue = dut.core.ieu.dp.regf.wd3;
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assign FPRAddr = dut.core.fpu.fpu.fregfile.a4;
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assign FPRWen = dut.core.fpu.fpu.fregfile.we4;
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assign FPRValue = dut.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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-----/\----- EXCLUDED -----/\----- */
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end
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//
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assign XLENZeros = '0;
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// start out easy and just populate Required
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