mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
35e31006a9
@ -6,6 +6,7 @@ add wave -noupdate /testbench/reset
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|||||||
add wave -noupdate /testbench/reset_ext
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add wave -noupdate /testbench/reset_ext
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||||||
add wave -noupdate -radix unsigned /testbench/InstrCountW
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add wave -noupdate -radix unsigned /testbench/InstrCountW
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||||||
add wave -noupdate /testbench/dut/hart/SATP_REGW
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add wave -noupdate /testbench/dut/hart/SATP_REGW
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||||||
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add wave -noupdate /testbench/dut/hart/IllegalFPUInstrD
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||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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||||||
@ -16,17 +17,19 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICa
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|||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/ExceptionM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrMisalignedFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrAccessFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ebreakM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/IllegalInstrFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadAccessFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ecallM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StoreMisalignedFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ExceptionM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrPageFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalCSRAccessM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadPageFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalFPUInstrM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StorePageFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/BreakpointFaultM
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||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/EcallFaultM
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||||||
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadMisalignedFaultM
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||||||
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StoreAccessFaultM
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||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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@ -37,11 +40,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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||||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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@ -119,12 +122,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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||||||
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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@ -167,35 +170,35 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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||||||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextF
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCPF
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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||||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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||||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
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||||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
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||||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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||||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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||||||
@ -228,138 +231,140 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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|||||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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||||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
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||||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
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||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MemAdrE_RENAME
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/IgnoreRequest
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ExceptionM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/IgnoreRequest
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ExceptionM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
@ -401,13 +406,13 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/har
|
|||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||||
@ -475,11 +480,11 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart
|
|||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK
|
add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HCLK
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HADDR
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
add wave -noupdate -expand -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
|
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
|
||||||
@ -508,8 +513,8 @@ add wave -noupdate /testbench/dut/hart/ifu/temp
|
|||||||
add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
|
add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
|
add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 9} {25261745 ns} 1} {{Cursor 10} {23549215 ns} 1} {{Cursor 11} {25261744 ns} 0}
|
WaveRestoreCursors {{Cursor 11} {37040373 ns} 1} {{Cursor 4} {37089727 ns} 1} {{Cursor 5} {37034476 ns} 1} {{Cursor 6} {37024155 ns} 0}
|
||||||
quietly wave cursor active 3
|
quietly wave cursor active 4
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 314
|
configure wave -valuecolwidth 314
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -524,4 +529,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {25261542 ns} {25261948 ns}
|
WaveRestoreZoom {37024043 ns} {37024259 ns}
|
||||||
|
|||||||
@ -1,66 +1,76 @@
|
|||||||
onerror {resume}
|
onerror {resume}
|
||||||
|
quietly virtual function -install /testbench/dut/hart/ifu -env /testbench/dut/hart/ifu { &{/testbench/dut/hart/ifu/BPPredWrongM, /testbench/dut/hart/ifu/InvalidateICacheM }} temp
|
||||||
quietly WaveActivateNextPane {} 0
|
quietly WaveActivateNextPane {} 0
|
||||||
add wave -noupdate /testbench/clk
|
add wave -noupdate /testbench/clk
|
||||||
add wave -noupdate /testbench/reset
|
add wave -noupdate /testbench/reset
|
||||||
add wave -noupdate /testbench/test
|
add wave -noupdate /testbench/reset_ext
|
||||||
add wave -noupdate /testbench/memfilename
|
add wave -noupdate /testbench/dut/hart/SATP_REGW
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/SATP_REGW
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||||
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/BreakpointFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ebreakM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/EcallFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ecallM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ExceptionM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalCSRAccessM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalFPUInstrM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/InstrAccessFaultM
|
||||||
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||||
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||||
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||||
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||||
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||||
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||||
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||||
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||||
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||||
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||||
|
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||||
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||||
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||||
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||||
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/InstrValidD
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
||||||
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
|
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||||
|
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
|
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
|
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
|
||||||
|
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
|
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
|
||||||
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
|
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||||
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
|
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
|
|
||||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
|
|
||||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
|
|
||||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
|
||||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
|
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
|
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
|
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
|
||||||
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
|
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
|
||||||
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
|
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
|
||||||
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
|
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
|
||||||
@ -97,12 +107,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
|
|||||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||||
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrW
|
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
|
||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
|
||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
|
||||||
@ -112,13 +122,7 @@ add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PC
|
|||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
|
||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
|
||||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
|
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
|
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
||||||
@ -151,103 +155,33 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
|||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||||
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||||
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
|
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
|
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
|
||||||
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
|
||||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
|
|
||||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
|
||||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
|
||||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||||
@ -269,136 +203,163 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
|||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||||
|
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct
|
||||||
|
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result
|
||||||
|
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
|
||||||
|
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
|
||||||
|
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
|
||||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
|
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
|
||||||
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/FetchCountFlag
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
|
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||||
@ -408,29 +369,36 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pm
|
|||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PhysicalAddress
|
||||||
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/ReadAccessM
|
||||||
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/WriteAccessM
|
||||||
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||||
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/Match
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/FirstMatch
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/R
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||||
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||||
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
|
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
|
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||||
@ -499,18 +467,31 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
|||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
|
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
|
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/WalkerPageFaultM
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
|
||||||
|
add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
|
||||||
|
add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/PCF
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/temp
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
|
||||||
|
add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {26646 ns} 1} {{Cursor 2} {70866 ns} 0} {{Cursor 3} {24171 ns} 1}
|
WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {26638 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 2
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 314
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
||||||
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
||||||
@ -523,4 +504,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {70741 ns} {70973 ns}
|
WaveRestoreZoom {26532 ns} {26750 ns}
|
||||||
|
|||||||
@ -176,7 +176,8 @@ module hptw
|
|||||||
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = FAULT;
|
//else NextWalkerState = FAULT;
|
||||||
|
else NextWalkerState = LEAF;
|
||||||
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = L1_ADR;
|
else NextWalkerState = L1_ADR;
|
||||||
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
@ -185,7 +186,8 @@ module hptw
|
|||||||
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = FAULT;
|
//else NextWalkerState = FAULT;
|
||||||
|
else NextWalkerState = LEAF;
|
||||||
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = L0_ADR;
|
else NextWalkerState = L0_ADR;
|
||||||
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||||
@ -193,14 +195,17 @@ module hptw
|
|||||||
// else NextWalkerState = FAULT;
|
// else NextWalkerState = FAULT;
|
||||||
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||||
else NextWalkerState = FAULT;
|
//else NextWalkerState = FAULT;
|
||||||
|
else NextWalkerState = LEAF;
|
||||||
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||||
// else NextWalkerState = FAULT;
|
// else NextWalkerState = FAULT;
|
||||||
LEAF: NextWalkerState = IDLE; // updates TLB
|
LEAF: NextWalkerState = IDLE; // updates TLB
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
|
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
|
||||||
else NextWalkerState = IDLE;
|
else NextWalkerState = IDLE;
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
default: begin
|
default: begin
|
||||||
// synthesis translate_off
|
// synthesis translate_off
|
||||||
$error("Default state in HPTW should be unreachable");
|
$error("Default state in HPTW should be unreachable");
|
||||||
|
|||||||
@ -103,11 +103,30 @@ module tlb #(parameter TLB_ENTRIES = 8,
|
|||||||
logic CAMHit;
|
logic CAMHit;
|
||||||
logic SV39Mode;
|
logic SV39Mode;
|
||||||
|
|
||||||
|
logic Misaligned;
|
||||||
|
logic MegapageMisaligned;
|
||||||
|
|
||||||
|
// Ross Thompson. If we are going to write invalid PTEs into the TLB should
|
||||||
|
// we cache Misaligned along with the PTE? This only has to be computed once
|
||||||
|
// in the hptw as it is always the same regardless of the VPN.
|
||||||
|
if(`XLEN == 32) begin
|
||||||
|
assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
|
||||||
|
assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
|
||||||
|
end else begin
|
||||||
|
logic GigapageMisaligned, TerapageMisaligned;
|
||||||
|
assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0
|
||||||
|
assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0
|
||||||
|
assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0
|
||||||
|
assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) |
|
||||||
|
((HitPageType == 2'b10) & GigapageMisaligned) |
|
||||||
|
((HitPageType == 2'b01) & MegapageMisaligned);
|
||||||
|
end
|
||||||
|
|
||||||
assign VPN = VAdr[`VPN_BITS+11:12];
|
assign VPN = VAdr[`VPN_BITS+11:12];
|
||||||
|
|
||||||
tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||||
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
|
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
|
||||||
.PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault,
|
.PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault,
|
||||||
.SV39Mode, .Translate);
|
.SV39Mode, .Translate);
|
||||||
|
|
||||||
tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
|
tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
|
||||||
|
|||||||
@ -43,6 +43,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
|||||||
input logic TLBFlush, // Invalidate all TLB entries
|
input logic TLBFlush, // Invalidate all TLB entries
|
||||||
input logic [7:0] PTEAccessBits,
|
input logic [7:0] PTEAccessBits,
|
||||||
input logic CAMHit,
|
input logic CAMHit,
|
||||||
|
input logic Misaligned,
|
||||||
output logic TLBMiss,
|
output logic TLBMiss,
|
||||||
output logic TLBHit,
|
output logic TLBHit,
|
||||||
output logic TLBPageFault,
|
output logic TLBPageFault,
|
||||||
@ -55,7 +56,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
|||||||
logic [`SVMODE_BITS-1:0] SVMode;
|
logic [`SVMODE_BITS-1:0] SVMode;
|
||||||
logic [1:0] EffectivePrivilegeMode;
|
logic [1:0] EffectivePrivilegeMode;
|
||||||
|
|
||||||
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
|
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
|
||||||
logic UpperBitsUnequalPageFault;
|
logic UpperBitsUnequalPageFault;
|
||||||
logic DAPageFault;
|
logic DAPageFault;
|
||||||
logic TLBAccess;
|
logic TLBAccess;
|
||||||
@ -85,7 +86,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
|||||||
|
|
||||||
// unswizzle useful PTE bits
|
// unswizzle useful PTE bits
|
||||||
assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
|
assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
|
||||||
assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1];
|
assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0];
|
||||||
|
|
||||||
// Check whether the access is allowed, page faulting if not.
|
// Check whether the access is allowed, page faulting if not.
|
||||||
generate
|
generate
|
||||||
@ -98,7 +99,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
|||||||
((EffectivePrivilegeMode == `S_MODE) && PTE_U);
|
((EffectivePrivilegeMode == `S_MODE) && PTE_U);
|
||||||
// fault for software handling if access bit is off
|
// fault for software handling if access bit is off
|
||||||
assign DAPageFault = ~PTE_A;
|
assign DAPageFault = ~PTE_A;
|
||||||
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault);
|
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||||
end else begin // Data TLB fault checking
|
end else begin // Data TLB fault checking
|
||||||
logic ImproperPrivilege, InvalidRead, InvalidWrite;
|
logic ImproperPrivilege, InvalidRead, InvalidWrite;
|
||||||
|
|
||||||
@ -115,7 +116,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
|||||||
assign InvalidWrite = WriteAccess && ~PTE_W;
|
assign InvalidWrite = WriteAccess && ~PTE_W;
|
||||||
// Fault for software handling if access bit is off or writing a page with dirty bit off
|
// Fault for software handling if access bit is off or writing a page with dirty bit off
|
||||||
assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D;
|
assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D;
|
||||||
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite || DAPageFault || UpperBitsUnequalPageFault);
|
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user