mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Changed testbench to use fopen instead of opening and closing uartfile whenever writing
This commit is contained in:
parent
770d918268
commit
354d447269
@ -256,6 +256,7 @@ module testbench;
|
|||||||
|
|
||||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
|
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
|
||||||
integer begin_signature_addr, end_signature_addr, signature_size;
|
integer begin_signature_addr, end_signature_addr, signature_size;
|
||||||
|
integer uartoutfile;
|
||||||
|
|
||||||
assign ResetThreshold = 3'd5;
|
assign ResetThreshold = 3'd5;
|
||||||
|
|
||||||
@ -355,8 +356,7 @@ module testbench;
|
|||||||
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||||
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||||
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
||||||
rmCmd = {"rm -f ", uartoutfilename};
|
uartoutfile = $fopen(uartoutfilename, "wb");
|
||||||
unused_int = system(rmCmd); // Delete existing UARToutfile
|
|
||||||
end
|
end
|
||||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||||
if (riscofTest) begin
|
if (riscofTest) begin
|
||||||
@ -383,6 +383,8 @@ module testbench;
|
|||||||
always @(posedge Validate) // added
|
always @(posedge Validate) // added
|
||||||
`endif
|
`endif
|
||||||
if(Validate) begin
|
if(Validate) begin
|
||||||
|
if (TEST == "buildroot")
|
||||||
|
$fclose(uartoutfile);
|
||||||
if (TEST == "embench") begin
|
if (TEST == "embench") begin
|
||||||
// Writes contents of begin_signature to .sim.output file
|
// Writes contents of begin_signature to .sim.output file
|
||||||
// this contains instret and cycles for start and end of test run, used by embench
|
// this contains instret and cycles for start and end of test run, used by embench
|
||||||
@ -602,9 +604,7 @@ module testbench;
|
|||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (TEST == "buildroot") begin
|
if (TEST == "buildroot") begin
|
||||||
if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
|
if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
|
||||||
memFile = $fopen(uartoutfilename, "ab");
|
$fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
|
||||||
$fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
|
|
||||||
$fclose(memFile);
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
Loading…
Reference in New Issue
Block a user