From 354d4472693c5c4fc2987b91ce0c223e6423ea47 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 16:56:54 -0700 Subject: [PATCH] Changed testbench to use fopen instead of opening and closing uartfile whenever writing --- testbench/testbench.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index cf87222c3..28537e4ec 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -256,6 +256,7 @@ module testbench; string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; integer begin_signature_addr, end_signature_addr, signature_size; + integer uartoutfile; assign ResetThreshold = 3'd5; @@ -355,8 +356,7 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/", TEST, "_uart.out"}; - rmCmd = {"rm -f ", uartoutfilename}; - unused_int = system(rmCmd); // Delete existing UARToutfile + uartoutfile = $fopen(uartoutfilename, "wb"); end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -383,6 +383,8 @@ module testbench; always @(posedge Validate) // added `endif if(Validate) begin + if (TEST == "buildroot") + $fclose(uartoutfile); if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file // this contains instret and cycles for start and end of test run, used by embench @@ -602,9 +604,7 @@ module testbench; always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin - memFile = $fopen(uartoutfilename, "ab"); - $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); - $fclose(memFile); + $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); end end end