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Generalize tlb module

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- number of tlb entries is now parameterized
- tlb now supports rv64i
This commit is contained in:
Thomas Fleming 2021-03-04 01:13:31 -05:00
parent 21552eaf9d
commit 347275e7ee
2 changed files with 115 additions and 87 deletions
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23
wally-pipelined/src/tlb_toy/tlb_testbench.sv
View File

@ -2,19 +2,22 @@ module testbench();
logic clk, reset; logic clk, reset;
// DUT inputs // DUT inputs
logic [31:0] PCF; logic [`XLEN-1:0] SATP;
logic [31:0] PageTableEntryF; logic [`XLEN-1:0] VirtualAddress;
logic ITLBWriteF, ITLBFlushF; logic [`XLEN-1:0] PageTableEntryWrite;
logic TLBWrite, TLBFlush;
// DUT outputs // DUT outputs
logic [31:0] PCPF; logic [`XLEN-1:0] PhysicalAddress;
logic ITLBMissF, ITLBHitF; logic TLBMiss, TLBHit;
// Testbench signals // Testbench signals
logic [33:0] expected; logic [33:0] expected;
logic [31:0] vectornum, errors; logic [31:0] vectornum, errors;
logic [99:0] testvectors[10000:0]; logic [99:0] testvectors[10000:0];
assign SATP = {1'b1, 31'b0};
// instantiate device under test // instantiate device under test
tlb_toy dut(.*); tlb_toy dut(.*);
@ -31,17 +34,17 @@ module testbench();
// apply test vectors on rising edge of clk // apply test vectors on rising edge of clk
always @(posedge clk) begin always @(posedge clk) begin
#1; {PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, expected} = testvectors[vectornum]; #1; {VirtualAddress, PageTableEntryWrite, TLBWrite, TLBFlush, expected} = testvectors[vectornum];
end end
// check results on falling edge of clk // check results on falling edge of clk
always @(negedge clk) always @(negedge clk)
if (~reset) begin // skip during reset if (~reset) begin // skip during reset
if ({PCPF, ITLBMissF, ITLBHitF} !== expected) begin // check result if ({PhysicalAddress, TLBMiss, TLBHit} !== expected) begin // check result
$display("Error: PCF = %b, write = %b, data = %b, flush = %b", PCF, $display("Error: VirtualAddress = %b, write = %b, data = %b, flush = %b", VirtualAddress,
ITLBWriteF, PageTableEntryF, ITLBFlushF); TLBWrite, PageTableEntryWrite, TLBFlush);
$display(" outputs = %b %b %b (%b expected)", $display(" outputs = %b %b %b (%b expected)",
PCPF, ITLBMissF, ITLBHitF, expected); PhysicalAddress, TLBMiss, TLBHit, expected);
errors = errors + 1; errors = errors + 1;
end end
vectornum = vectornum + 1; vectornum = vectornum + 1;

173
wally-pipelined/src/tlb_toy/tlb_toy.sv
View File

@ -24,7 +24,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
// `include "wally-config.vh" `include "wally-config.vh"
/** /**
* sv32 specs * sv32 specs
@ -49,126 +49,159 @@
/* *** TODO: /* *** TODO:
* - add LRU algorithm (select the write index based on which entry was used * - add LRU algorithm (select the write index based on which entry was used
* least recently) * least recently)
* - rename signals to use .* notation in CAM and RAM
*/ */
module tlb_toy ( // The TLB will have 2**ENTRY_BITS total entries
module tlb_toy #(parameter ENTRY_BITS = 3) (
input clk, reset, input clk, reset,
// Current value of satp CSR (from privileged unit)
input [`XLEN-1:0] SATP, // *** How do we get this?
// Virtual address input // Virtual address input
input [31:0] PCF, input [`XLEN-1:0] VirtualAddress,
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
input [31:0] PageTableEntryF, input [`XLEN-1:0] PageTableEntryWrite,
input ITLBWriteF, input TLBWrite,
// Invalidate all TLB entries // Invalidate all TLB entries
input ITLBFlushF, input TLBFlush,
// Physical address outputs // Physical address outputs
output [31:0] PCPF, output [`XLEN-1:0] PhysicalAddress,
output ITLBMissF, output TLBMiss,
output ITLBHitF output TLBHit
); );
generate
if (`XLEN == 32) begin: ARCH
localparam VPN_BITS = 20;
localparam PPN_BITS = 22;
localparam PA_BITS = 34;
logic SvMode;
assign SvMode = SATP[31]; // *** change to an enum somehow?
end else begin: ARCH
localparam VPN_BITS = 27;
localparam PPN_BITS = 44;
localparam PA_BITS = 56;
logic SvMode; // currently just a boolean whether translation enabled
assign SvMode = SATP[63]; // *** change to an enum somehow?
end
endgenerate
// Index (currently random) to write the next TLB entry // Index (currently random) to write the next TLB entry
logic [2:0] WriteIndexF; logic [ENTRY_BITS-1:0] WriteIndex;
// Sections of the virtual and physical addresses // Sections of the virtual and physical addresses
logic [19:0] VirtualPageNumberF; logic [ARCH.VPN_BITS-1:0] VirtualPageNumber;
logic [21:0] PhysicalPageNumberF; logic [ARCH.PPN_BITS-1:0] PhysicalPageNumber;
logic [11:0] PageOffsetF; logic [11:0] PageOffset;
logic [33:0] PhysicalAddressF; logic [ARCH.PA_BITS-1:0] PhysicalAddressFull;
// Pattern and pattern location in the CAM // Pattern and pattern location in the CAM
logic [2:0] VPNIndexF; logic [ENTRY_BITS-1:0] VPNIndex;
// RAM access location // RAM access location
logic [2:0] ITLBEntryIndex; logic [ENTRY_BITS-1:0] EntryIndex;
// Page table entry matching the virtual address // Page table entry matching the virtual address
logic [31:0] PTEMatchF; logic [`XLEN-1:0] PageTableEntry;
assign VirtualPageNumberF = PCF[31:12]; assign VirtualPageNumber = VirtualAddress[ARCH.VPN_BITS+11:12];
assign PageOffsetF = PCF[11:0]; assign PageOffset = VirtualAddress[11:0];
// Choose a read or write location to the entry list // Choose a read or write location to the entry list
mux2 #(3) indexmux(VPNIndexF, WriteIndexF, ITLBWriteF, ITLBEntryIndex); mux2 #(3) indexmux(VPNIndex, WriteIndex, TLBWrite, EntryIndex);
// Currently use random replacement algorithm // Currently use random replacement algorithm
rand3 rdm(clk, reset, WriteIndexF); tlb_rand rdm(.*);
ram8x32 ram(clk, reset, ITLBEntryIndex, PageTableEntryF, ITLBWriteF, PTEMatchF); tlb_ram #(ENTRY_BITS) ram(.*);
cam8x21 cam(clk, reset, ITLBWriteF, VirtualPageNumberF, WriteIndexF, tlb_cam #(ENTRY_BITS, ARCH.VPN_BITS) cam(.*);
ITLBFlushF, VPNIndexF, ITLBHitF);
always_comb begin always_comb begin
assign PhysicalPageNumberF = PTEMatchF[31:10]; assign PhysicalPageNumber = PageTableEntry[ARCH.PPN_BITS+9:10];
if (ITLBHitF) begin if (TLBHit) begin
assign PhysicalAddressF = {PhysicalPageNumberF, PageOffsetF}; assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
end else begin end else begin
assign PhysicalAddressF = 34'b0; assign PhysicalAddressFull = 8'b0; // *** Actual behavior; disabled until walker functioning
//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
end end
end end
assign PCPF = PhysicalAddressF[31:0]; generate
assign ITLBMissF = ~ITLBHitF & ~(ITLBWriteF | ITLBFlushF); if (`XLEN == 32) begin
mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], ARCH.SvMode, PhysicalAddress);
end else begin
mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, ARCH.SvMode, PhysicalAddress);
end
endgenerate
assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & ARCH.SvMode;
endmodule endmodule
// *** Add parameter for number of tlb lines (currently 8) module tlb_ram #(parameter ENTRY_BITS = 3) (
module ram8x32 (
input clk, reset, input clk, reset,
input [2:0] address, input [ENTRY_BITS-1:0] EntryIndex,
input [31:0] data, input [`XLEN-1:0] PageTableEntryWrite,
input we, input TLBWrite,
output [31:0] out_data output [`XLEN-1:0] PageTableEntry
); );
logic [31:0] ram [0:7]; localparam NENTRIES = 2**ENTRY_BITS;
logic [`XLEN-1:0] ram [0:NENTRIES-1];
always @(posedge clk) begin always @(posedge clk) begin
if (we) ram[address] <= data; if (TLBWrite) ram[EntryIndex] <= PageTableEntryWrite;
end end
assign out_data = ram[address]; assign PageTableEntry = ram[EntryIndex];
initial begin initial begin
for (int i = 0; i < 8; i++) for (int i = 0; i < NENTRIES; i++)
ram[i] = 32'h0; ram[i] = `XLEN'b0;
end end
endmodule endmodule
module cam8x21 ( module tlb_cam #(parameter ENTRY_BITS = 3,
input clk, reset, we, parameter KEY_BITS = 20) (
input [19:0] pattern, input clk, reset,
input [2:0] write_address, input [KEY_BITS-1:0] VirtualPageNumber,
input ITLBFlushF, input [ENTRY_BITS-1:0] WriteIndex,
output [2:0] matched_address, input TLBWrite,
output match_found input TLBFlush,
output [ENTRY_BITS-1:0] VPNIndex,
output TLBHit
); );
logic [20:0] ram [0:7]; localparam NENTRIES = 2**ENTRY_BITS;
logic [7:0] match_line;
logic [2:0] matched_address_comb; // Each entry of this memory has KEY_BITS for the key plus one valid bit.
logic [KEY_BITS:0] ram [0:NENTRIES-1];
logic [ENTRY_BITS-1:0] matched_address_comb;
logic match_found_comb; logic match_found_comb;
always @(posedge clk) begin always @(posedge clk) begin
if (we) ram[write_address] <= {1'b1,pattern}; if (TLBWrite) ram[WriteIndex] <= {1'b1,VirtualPageNumber};
if (ITLBFlushF) begin if (TLBFlush) begin
for (int i = 0; i < 8; i++) for (int i = 0; i < NENTRIES; i++)
ram[i][20] = 1'b0; ram[i][KEY_BITS] = 1'b0; // Zero out msb (valid bit) of all entries
end end
end end
// *** Check whether this for loop synthesizes correctly // *** Check whether this for loop synthesizes correctly
always_comb begin always_comb begin
match_found_comb = 1'b0; match_found_comb = 1'b0;
matched_address_comb = 3'b0; matched_address_comb = '0;
for (int i = 0; i < 8; i++) begin for (int i = 0; i < NENTRIES; i++) begin
if (ram[i] == {1'b1,pattern} && !match_found_comb) begin if (ram[i] == {1'b1,VirtualPageNumber} && !match_found_comb) begin
matched_address_comb = i; matched_address_comb = i;
match_found_comb = 1; match_found_comb = 1;
end else begin end else begin
@ -178,31 +211,23 @@ module cam8x21 (
end end
end end
assign matched_address = matched_address_comb; assign VPNIndex = matched_address_comb;
assign match_found = match_found_comb & ~(we | ITLBFlushF); assign TLBHit = match_found_comb & ~(TLBWrite | TLBFlush);
initial begin initial begin
for (int i = 0; i < 8; i++) for (int i = 0; i < NENTRIES; i++)
ram[i] <= 0; ram[i] <= '0;
end end
endmodule endmodule
module mux2 #(parameter WIDTH = 8) ( module tlb_rand #(parameter ENTRY_BITS = 3) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module rand3 (
input clk, reset, input clk, reset,
output [2:0] WriteIndexF output [ENTRY_BITS:0] WriteIndex
); );
logic [31:0] data; logic [31:0] data;
assign data = $urandom; assign data = $urandom;
assign WriteIndexF = data[2:0]; assign WriteIndex = data[ENTRY_BITS:0];
endmodule endmodule