mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
3308550409
@ -2,10 +2,14 @@
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// spi_apb.sv
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//
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// Written: Naiche Whyte-Aguayo nwhyteaguayo@g.hmc.edu 11/16/2022
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//
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// Purpose: SPI peripheral
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// See FU540-C000-v1.0 for specifications
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//
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// SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
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// The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
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// to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output,
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// along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
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// Current limitations: Flash read sequencer mode not implemented, dual and quad mode not supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -25,19 +29,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
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// Attempt to move from >= comparisons by initializing in FSM differently
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// Parameterize SynchFIFO
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// look at ReadIncrement/WriteIncrement delay necessity
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/*
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SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
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The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
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to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output,
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along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
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*/
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module spi_apb import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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@ -83,12 +74,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
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logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData;
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logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
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logic [7:0] ReceiveShiftRegEndian; //reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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// Transmission signals
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logic sck;
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logic [11:0] DivCounter; //counter for sck
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logic SCLKenable; //flip flop enable high every sclk edge
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logic [11:0] DivCounter; // Counter for sck
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logic SCLKenable; // Flip flop enable high every sclk edge
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// Delay signals
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logic [8:0] ImplicitDelay1; // Adds implicit delay to cs-sck delay counter based on phase
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@ -97,18 +88,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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logic [8:0] SCK_CSCount; // Counter for sck-cs delay
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logic [8:0] InterCSCount; // Counter for inter cs delay
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logic [8:0] InterXFRCount; // Counter for inter xfr delay
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logic CS_SCKCompare; //Boolean comparison signal, high when CS_SCKCount >= cs-sck delay
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logic SCK_CSCompare; //Boolean comparison signal, high when SCK_CSCount >= sck-cs delay
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logic InterCSCompare; //Boolean comparison signal, high when InterCSCount >= inter cs delay
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logic InterXFRCompare; //Boolean comparison signal, high when InterXFRCount >= inter xfr delay
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logic ZeroDelayHoldMode; // High when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// Frame counting signals
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logic [3:0] FrameCount; // Counter for number of frames in transmission
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logic FrameCompare; //Boolean comparison signal, high when FrameCount = Format[7:4]
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logic [3:0] ReceivePenultimateFrame; //Frame number - 1
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logic [3:0] ReceivePenultimateFrameCount; // Counter
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logic ReceivePenultimateFrameBoolean; //High when penultimate frame in transmission has been reached
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logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
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// State fsm signals
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logic Active; // High when state is either Active1 or Active0 (during transmission)
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@ -134,15 +119,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// Miscellaneous signals delayed/early by 1 PCLK cycle
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logic ReceiveShiftFullDelay; // Delays ReceiveShiftFull signal by 1 PCLK cycle
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logic TransmitFIFOWriteIncrementDelay; //TransmitFIFOWriteIncrement delayed by 1 PCLK cycle
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logic ReceiveShiftFullDelayPCLK; // ReceiveShiftFull delayed by 1 PCLK cycle
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logic TransmitFIFOReadEmptyDelay;
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logic SCLKenableEarly; // SCLKenable 1 PCLK cycle early, needed for on time register changes when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// APB access
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = TransmitInactive; // tie PREADY to transmission for hardware interlock
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assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
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assign PREADY = TransmitInactive; // Tie PREADY to transmission for hardware interlock
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// Account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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@ -168,8 +152,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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InterruptEnable <= #1 2'b0;
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InterruptPending <= #1 2'b0;
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end else begin // writes
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//According to FU540 spec: Once interrupt is pending, it will remain set until number
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//of entries in tx/rx fifo is strictly more/less than tx/rxmark
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/* verilator lint_off CASEINCOMPLETE */
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if (Memwrite & TransmitInactive)
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@ -188,18 +171,21 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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8'h70: InterruptEnable <= Din[1:0];
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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//interrupt clearance
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// According to FU540 spec: Once interrupt is pending, it will remain set until number
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// of entries in tx/rx fifo is strictly more/less than tx/rxmark
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InterruptPending[0] <= TransmitReadMark;
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InterruptPending[1] <= RecieveWriteMark;
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case(Entry) // flop to sample inputs
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case(Entry) // Flop to sample inputs
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8'h00: Dout <= #1 {20'b0, SckDiv};
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8'h04: Dout <= #1 {30'b0, SckMode};
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8'h10: Dout <= #1 {30'b0, ChipSelectID};
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8'h14: Dout <= #1 {28'b0, ChipSelectDef};
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8'h18: Dout <= #1 {30'b0, ChipSelectMode};
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8'h28: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
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8'h2C: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
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8'h40: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
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8'h28: Dout <= #1 {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
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8'h2C: Dout <= #1 {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
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8'h40: Dout <= #1 {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
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8'h48: Dout <= #1 {23'b0, TransmitFIFOWriteFull, 8'b0};
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8'h4C: Dout <= #1 {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
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8'h50: Dout <= #1 {29'b0, TransmitWatermark};
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@ -211,7 +197,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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//Generates a high signal at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
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assign SCLKenable = (DivCounter == SckDiv);
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assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
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always_ff @(posedge PCLK, negedge PRESETn)
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@ -219,44 +206,38 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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else if (SCLKenable) DivCounter <= 0;
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else DivCounter <= DivCounter + 12'b1;
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//Boolean logic that tracks frame progression
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assign FrameCompare = (FrameCount < Format[4:1]);
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assign ReceivePenultimateFrameBoolean = ((FrameCount + 4'b0001) == Format[4:1]);
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// Asserts when transmission is one frame before complete
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assign ReceivePenultimateFrame = ((FrameCount + 4'b0001) == Format[4:1]);
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// Computing delays
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// When sckmode.pha = 0, an extra half-period delay is implicit in the cs-sck delay, and vice-versa for sck-cs
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assign ImplicitDelay1 = SckMode[0] ? 9'b0 : 9'b1;
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assign ImplicitDelay2 = SckMode[0] ? 9'b1 : 9'b0;
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assign CS_SCKCompare = CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1);
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assign SCK_CSCompare = SCK_CSCount >= (({Delay0[15:8], 1'b0}) + ImplicitDelay2);
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assign InterCSCompare = (InterCSCount >= ({Delay1[7:0],1'b0}));
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assign InterXFRCompare = (InterXFRCount >= ({Delay1[15:8], 1'b0}));
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// Calculate when tx/rx shift registers are full/empty
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TransmitShiftFSM TransmitShiftFSM_1 (PCLK, PRESETn, TransmitFIFOReadEmpty, ReceivePenultimateFrameBoolean, Active0, TransmitShiftEmpty);
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ReceiveShiftFSM ReceiveShiftFSM_1 (PCLK, PRESETn, SCLKenable, ReceivePenultimateFrameBoolean, SampleEdge, SckMode[0], ReceiveShiftFull);
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TransmitShiftFSM TransmitShiftFSM(PCLK, PRESETn, TransmitFIFOReadEmpty, ReceivePenultimateFrame, Active0, TransmitShiftEmpty);
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ReceiveShiftFSM ReceiveShiftFSM(PCLK, PRESETn, SCLKenable, ReceivePenultimateFrame, SampleEdge, SckMode[0], ReceiveShiftFull);
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// Calculate tx/rx fifo write and recieve increment signals
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assign TransmitFIFOWriteIncrement = (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) TransmitFIFOWriteIncrementDelay <= 0;
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else TransmitFIFOWriteIncrementDelay <= TransmitFIFOWriteIncrement;
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if (~PRESETn) TransmitFIFOWriteIncrement <= 0;
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else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) ReceiveFIFOReadIncrement <= 0;
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else ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
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// Tx/Rx FIFOs
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SynchFIFO #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrementDelay, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0], TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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SynchFIFO #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
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SynchFIFO #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
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TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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SynchFIFO #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
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ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1;
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else if (SCLKenable) TransmitFIFOReadEmptyDelay <= TransmitFIFOReadEmpty;
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) ReceiveShiftFullDelay <= 0;
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else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
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@ -271,11 +252,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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statetype state;
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) begin state <= CS_INACTIVE;
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if (~PRESETn) begin
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state <= CS_INACTIVE;
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FrameCount <= 4'b0;
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/* verilator lint_off CASEINCOMPLETE */
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end else if (SCLKenable) begin
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/* verilator lint_off CASEINCOMPLETE */
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case (state)
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CS_INACTIVE: begin
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CS_SCKCount <= 9'b1;
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@ -288,7 +269,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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DELAY_0: begin
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CS_SCKCount <= CS_SCKCount + 9'b1;
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if (CS_SCKCompare) state <= ACTIVE_0;
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if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) state <= ACTIVE_0;
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end
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ACTIVE_0: begin
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FrameCount <= FrameCount + 4'b1;
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@ -296,7 +277,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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ACTIVE_1: begin
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InterXFRCount <= 9'b1;
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if (FrameCompare) state <= ACTIVE_0;
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if (FrameCount < Format[4:1]) state <= ACTIVE_0;
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else if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty)) begin
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state <= ACTIVE_0;
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CS_SCKCount <= 9'b1;
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@ -310,11 +291,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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end
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DELAY_1: begin
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SCK_CSCount <= SCK_CSCount + 9'b1;
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if (SCK_CSCompare) state <= INTER_CS;
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if (SCK_CSCount >= (({Delay0[15:8], 1'b0}) + ImplicitDelay2)) state <= INTER_CS;
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end
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INTER_CS: begin
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InterCSCount <= InterCSCount + 9'b1;
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if (InterCSCompare ) state <= CS_INACTIVE;
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if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE;
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end
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INTER_XFR: begin
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CS_SCKCount <= 9'b1;
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@ -322,13 +303,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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InterXFRCount <= InterXFRCount + 9'b1;
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if (InterXFRCompare & ~TransmitFIFOReadEmptyDelay) state <= ACTIVE_0;
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if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) state <= ACTIVE_0;
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else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
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end
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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end
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/* verilator lint_off CASEINCOMPLETE */
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assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
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assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
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@ -390,7 +372,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
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endmodule
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|
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module SynchFIFO #(parameter M =3 , N= 8)(
|
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module SynchFIFO #(parameter M=3, N=8)( // 2^M entries of N bits each
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input logic PCLK, wen, ren, PRESETn,
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input logic winc, rinc,
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input logic [N-1:0] wdata,
|
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@ -409,8 +391,6 @@ module SynchFIFO #(parameter M =3 , N= 8)(
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logic [N-1:0] mem[2**M];
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logic [M:0] rptr, wptr;
|
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logic [M:0] rptrnext, wptrnext;
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logic rempty_val;
|
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logic wfull_val;
|
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logic [M-1:0] raddr;
|
||||
logic [M-1:0] waddr;
|
||||
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@ -428,53 +408,43 @@ module SynchFIFO #(parameter M =3 , N= 8)(
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||||
end
|
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else begin
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||||
if (wen) begin
|
||||
wfull <= wfull_val;
|
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wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
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wptr <= wptrnext;
|
||||
end
|
||||
if (ren) begin
|
||||
rptr <= rptrnext;
|
||||
rempty <= rempty_val;
|
||||
rempty <= (wptr == rptrnext);
|
||||
end
|
||||
end
|
||||
|
||||
assign raddr = rptr[M-1:0];
|
||||
assign rptrnext = rptr + {3'b0, (rinc & ~rempty)};
|
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assign rempty_val = (wptr == rptrnext);
|
||||
assign rptrnext = rptr + {{(M){1'b0}}, (rinc & ~rempty)};
|
||||
assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull;
|
||||
assign waddr = wptr[M-1:0];
|
||||
assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull;
|
||||
assign wptrnext = wptr + {3'b0, (winc & ~wfull)};
|
||||
assign wfull_val = ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
|
||||
assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)};
|
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endmodule
|
||||
|
||||
module TransmitShiftFSM(
|
||||
input logic PCLK, PRESETn,
|
||||
input logic TransmitFIFOReadEmpty, ReceivePenultimateFrameBoolean, Active0,
|
||||
input logic TransmitFIFOReadEmpty, ReceivePenultimateFrame, Active0,
|
||||
output logic TransmitShiftEmpty);
|
||||
|
||||
typedef enum logic [1:0] {TransmitShiftEmptyState, TransmitShiftHoldState, TransmitShiftNotEmptyState} statetype;
|
||||
statetype TransmitState, TransmitNextState;
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
if (~PRESETn) TransmitState <= TransmitShiftEmptyState;
|
||||
else TransmitState <= TransmitNextState;
|
||||
if (~PRESETn) TransmitShiftEmpty <= 1;
|
||||
else if (TransmitShiftEmpty) begin
|
||||
if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1;
|
||||
else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 0;
|
||||
end else begin
|
||||
if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1;
|
||||
else TransmitShiftEmpty <= 0;
|
||||
end
|
||||
|
||||
always_comb
|
||||
case(TransmitState)
|
||||
TransmitShiftEmptyState: begin
|
||||
if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrameBoolean & Active0))) TransmitNextState = TransmitShiftEmptyState;
|
||||
else if (~TransmitFIFOReadEmpty) TransmitNextState = TransmitShiftNotEmptyState;
|
||||
end
|
||||
TransmitShiftNotEmptyState: begin
|
||||
if (ReceivePenultimateFrameBoolean & Active0) TransmitNextState = TransmitShiftEmptyState;
|
||||
else TransmitNextState = TransmitShiftNotEmptyState;
|
||||
end
|
||||
endcase
|
||||
assign TransmitShiftEmpty = (TransmitNextState == TransmitShiftEmptyState);
|
||||
endmodule
|
||||
|
||||
module ReceiveShiftFSM(
|
||||
input logic PCLK, PRESETn, SCLKenable,
|
||||
input logic ReceivePenultimateFrameBoolean, SampleEdge, SckMode,
|
||||
input logic ReceivePenultimateFrame, SampleEdge, SckMode,
|
||||
output logic ReceiveShiftFull
|
||||
);
|
||||
typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} statetype;
|
||||
@ -484,7 +454,7 @@ module ReceiveShiftFSM(
|
||||
else if (SCLKenable) begin
|
||||
case (ReceiveState)
|
||||
ReceiveShiftFullState: ReceiveState <= ReceiveShiftNotFullState;
|
||||
ReceiveShiftNotFullState: if (ReceivePenultimateFrameBoolean & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
|
||||
ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
|
||||
else ReceiveState <= ReceiveShiftNotFullState;
|
||||
ReceiveShiftDelayState: ReceiveState <= ReceiveShiftFullState;
|
||||
endcase
|
||||
@ -493,8 +463,3 @@ module ReceiveShiftFSM(
|
||||
assign ReceiveShiftFull = SckMode ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState);
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user