From 32c102d89a493133e4fa843e330e43a6dc540cee Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 14:34:42 -0800 Subject: [PATCH] All deriv tests generated, use sim/make deriv --- bin/derivgen.pl | 19 +- config/buildroot/config.vh | 2 +- config/derivlist.txt | 441 +++++++++++++++++++++++++++++++++++- config/rv32e/config.vh | 5 + config/rv32gc/config.vh | 5 + config/rv32i/config.vh | 5 + config/rv32imc/config.vh | 5 + config/rv64fpquad/config.vh | 5 + config/rv64gc/config.vh | 6 + config/rv64i/config.vh | 5 + sim/Makefile | 6 +- sim/lint-wally | 4 +- 12 files changed, 498 insertions(+), 10 deletions(-) diff --git a/bin/derivgen.pl b/bin/derivgen.pl index 6fe84fdfe..096918400 100755 --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -34,6 +34,7 @@ use strict; use warnings; import os; +use Data::Dumper; my $curderiv = ""; my @derivlist = (); @@ -61,7 +62,8 @@ foreach my $line (<$fh>) { @derivlist = @{$inherits}; } } else { # add to the current derivative - my @entry = ($tokens[0], $tokens[1]); + $line =~ /\s*(\S+)\s*(.*)/; + my @entry = ($1, $2); push(@derivlist, \@entry); } } @@ -79,21 +81,30 @@ foreach my $key (keys %derivs) { open(my $fh, '>>', $config) or die "Could not open file '$config' $!"; my $datestring = localtime(); + my %hit = (); print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; foreach my $line (<$unmod>) { foreach my $entry (@{$derivs{$key}}) { my @ent = @{$entry}; my $param = $ent[0]; my $value = $ent[1]; - if ($line =~ s/$param\s*=\s*.*;/$param = $value;/g) { - print("Hit: new line in $config is $line"); - #print $fh $line; + if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) { + $hit{$param} = 1; +# print("Hit: new line in $config for $param is $line"); } } print $fh $line; } close($fh); close($unmod); + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + if (!exists($hit{$param})) { + print("Unable to find $param in $key\n"); + } + } + system("rm -f $dir/config_unmod.vh"); } sub terminateDeriv { diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index de6e4800d..d334ab373 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -153,7 +153,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; - +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt index 0ba20e793..8b6eaf1d8 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -41,7 +41,7 @@ RESET_VECTOR 64'h1000 UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_PRELOAD 1 GPIO_LOOPBACK_TEST 0 -SPI_LOOBACK_TEST 0 +SPI_LOOPBACK_TEST 0 UART_PRESCALE 0 PLIC_NUM_SRC 32'd53 @@ -63,7 +63,6 @@ DTIM_RANGE 32'h1FF IROM_RANGE 32'h1FF BOOTROM_RANGE 32'h1FF UNCORE_RAM_RANGE 32'h1FF -BOOTROM_RANGE 32'h1FF WAYSIZEINBYTES 32'd512 NUMWAYS 32'd1 BPRED_SIZE 32'd5 @@ -76,3 +75,441 @@ deriv syn_rv32gc rv32gc syn_rv32e deriv syn_rv64i rv64i syn_rv32e deriv syn_rv64gc rv64gc syn_rv32e +# The syn_sram configurations use SRAM macros +deriv syn_sram_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +USE_SRAM 1 + +# The other syn configurations have the same trimming +deriv syn_sram_rv32i rv32i syn_sram_rv32e +deriv syn_sram_rv32imc rv32imc syn_sram_rv32e +deriv syn_sram_rv32gc rv32gc syn_sram_rv32e +deriv syn_sram_rv64i rv64i syn_sram_rv32e +deriv syn_sram_rv64gc rv64gc syn_sram_rv32e + +# The following syn configurations gradually turn off features +deriv syn_pmp0_rv64gc rv64gc syn_rv64gc +PMP_ENTRIES 0 +deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc +PMP_ENTRIES 0 + +deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc +ZICSR_SUPPORTED 0 +deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc +ZICSR_SUPPORTED 0 + +deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) + +deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) +deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) + +deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) +deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) + +# Divider variants to check logical correctness + +deriv div_2_1_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_1_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc +IDIV_ON_FPU 1 + +# RAM latency and Burst mode for bus stress testing + +deriv ram_0_0_rv64gc rv64gc +RAM_LATENCY 0 +BURST_EN 0 + +deriv ram_1_0_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 0 + +deriv ram_2_0_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 0 + +deriv ram_1_1_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 1 + +deriv ram_2_1_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 1 + +# Branch predictor simulations + +deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc +BPRED_SIZE 6 + +deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc +BPRED_SIZE 8 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +BPRED_SIZE 10 + +deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc +BPRED_SIZE 12 + +deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc +BPRED_SIZE 14 + +deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc +BPRED_SIZE 16 + +deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 2 + +deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc +RAS_SIZE 3 + +deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc +RAS_SIZE 4 + +deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc +RAS_SIZE 6 + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 10 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +RAS_SIZE 16 + +deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc +BTB_SIZE 6 + +deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc +BTB_SIZE 8 + +deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc +BTB_SIZE 12 + +deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc +BTB_SIZE 14 + +deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc +BTB_SIZE 16 + +deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc +ICLASSPRED 0 + +# Cache configurations + +deriv noicache_rv32gc rv32gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv32gc rv32gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv32gc rv32gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv32gc rv32gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +deriv noicache_rv64gc rv64gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv64gc rv64gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv64gc rv64gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +# TLB Size variants + +deriv tlb2_rv32gc rv32gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv32gc rv32gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +deriv tlb2_rv64gc rv64gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv64gc rv64gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +# Feature variants + +deriv misaligned_rv32gc rv32gc +ZICCLSM_SUPPORTED 1 + +deriv nomisaligned_rv64gc rv64gc +ZICCLSM_SUPPORTED 0 + +deriv nobigendian_rv32gc rv32gc +BIGENDIAN_SUPPORTED 0 + +deriv nobigendian_rv64gc rv64gc +BIGENDIAN_SUPPORTED 0 + +# Floating-point modes supported + +deriv f_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdq_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv f_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fd_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 70d455b4e..9abf11bf7 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 0; @@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 4baef0075..9a1ca7fea 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -133,6 +133,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -166,6 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 6e5d08803..a6ebe0985 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index a32dc3bd6..5d8a3690b 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -131,6 +131,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 09885808f..9a3416524 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 04a674b47..fa397471b 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; @@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0; localparam USE_SRAM = 0; `include "config-shared.vh" + diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 609a50f97..9061da2a5 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/sim/Makefile b/sim/Makefile index 5889d1df9..d7d259632 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles coveragetests +all: riscoftests memfiles coveragetests deriv # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -60,3 +60,7 @@ memfiles: coveragetests: make -C ../tests/coverage/ --jobs + +deriv: + derivgen.pl + \ No newline at end of file diff --git a/sim/lint-wally b/sim/lint-wally index eb6ad62b0..c82d1603b 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -5,10 +5,10 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do #for config in rv64gc; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi