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Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.

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Ross Thompson 2022-12-23 11:45:42 -06:00
parent 98ecd9c77d
commit 30dd86d146
1 changed files with 1 additions and 1 deletions
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pipelined/src/ieu/forward.sv
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@ -57,7 +57,7 @@ module forward(
end end
// Stall on dependent operations that finish in Mem Stage and can't bypass in time // Stall on dependent operations that finish in Mem Stage and can't bypass in time
assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
assign LoadStallD = (MemReadE|SCE) & MatchDE; assign LoadStallD = (MemReadE|SCE) & MatchDE;
assign MDUStallD = MDUE & MatchDE; assign MDUStallD = MDUE & MatchDE;