From 30dd86d146ad6c9988f21a7a656e4316826534e4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 23 Dec 2022 11:45:42 -0600 Subject: [PATCH] Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. --- pipelined/src/ieu/forward.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index da68307c0..701a7d431 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -57,7 +57,7 @@ module forward( end // Stall on dependent operations that finish in Mem Stage and can't bypass in time - assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction + assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt assign LoadStallD = (MemReadE|SCE) & MatchDE; assign MDUStallD = MDUE & MatchDE;