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https://github.com/openhwgroup/cvw
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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
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@ -46,7 +46,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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// performance counter logging
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// performance counter logging
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logic BeginSample;
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logic BeginSample;
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logic StartSample, EndSample;
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logic StartSample, EndSample;
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if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
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if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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logic StartSampleDelayed, BeginDelayed;
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@ -94,15 +94,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
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EndSampleFirst = '0;
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EndSampleFirst = '0;
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end
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end
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// this code needs to be with embench and coremark but not the else condition
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/* -----\/----- EXCLUDED -----\/-----
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if (TEST == "embench" | TEST == "coremark") begin
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end
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-----/\----- EXCLUDED -----/\----- */
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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always_comb
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always_comb
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if (TEST == "embench" | TEST == "coremark") begin
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if (TEST == "embench" | TEST == "coremark") begin
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