From 2fe73f8174a5a860ef7e5d89a80b56d7f39c62ac Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 13 Nov 2024 00:02:51 -0600 Subject: [PATCH] Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore. --- testbench/common/loggers.sv | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 287d02346..0bd0f00a7 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -46,7 +46,7 @@ module loggers import cvw::*; #(parameter cvw_t P, // performance counter logging logic BeginSample; logic StartSample, EndSample; - if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample + if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; @@ -94,15 +94,6 @@ module loggers import cvw::*; #(parameter cvw_t P, EndSampleFirst = '0; end - // this code needs to be with embench and coremark but not the else condition -/* -----\/----- EXCLUDED -----\/----- - if (TEST == "embench" | TEST == "coremark") begin - assign EndSample = EndSampleFirst & ~ EndSampleDelayed; - end else begin - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; - end - -----/\----- EXCLUDED -----/\----- */ - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); always_comb if (TEST == "embench" | TEST == "coremark") begin