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added missing output for sret

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Kip Macsai-Goren 2022-04-27 18:19:08 +00:00
parent 746fcfde30
commit 2f17edb5f4
1 changed files with 3 additions and 3 deletions
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
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@ -4,6 +4,9 @@
00000002 # mcause for illegal sret instruction due to status.tsr bit being set. 00000002 # mcause for illegal sret instruction due to status.tsr bit being set.
10200073 # mtval of illegal instruction (illegal instruction's machine code) 10200073 # mtval of illegal instruction (illegal instruction's machine code)
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
00000009 # mcause from S mode ecall from test termination
00000000 # mtval of ecall (*** defined to be zero for now)
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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