diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
index 7d62f0bb9..f5d842bf5 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
@@ -4,6 +4,9 @@
 00000002 # mcause for illegal sret instruction due to status.tsr bit being set.
 10200073 # mtval of illegal instruction (illegal instruction's machine code)
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000009 # mcause from S mode ecall from test termination
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
 deadbeef
 deadbeef
 deadbeef
@@ -1019,6 +1022,3 @@ deadbeef
 deadbeef
 deadbeef
 deadbeef
-deadbeef
-deadbeef
-deadbeef