Merge branch 'main' of github.com:rosethompson/cvw

2025-02-02 17:55:19 +00:00 · 2024-11-25 15:53:27 -06:00 · 2024-11-25 15:53:27 -06:00 · 2f04e5e597
commit 2f04e5e597
parent 7358c1fe67 486d1dbf33
54 changed files with 707 additions and 486 deletions
--- a/.github/dependabot.yml
+++ b/.github/dependabot.yml
@ -0,0 +1,17 @@
+# To get started with Dependabot version updates, you'll need to specify which
+# package ecosystems to update and where the package manifests are located.
+# Please see the documentation for all configuration options:
+# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file
+
+version: 2
+updates:
+  # Update git submodules to latest version
+  - package-ecosystem: "gitsubmodule"
+    directory: "/"
+    schedule:
+      interval: "weekly"
+  # Update actions in the GitHub Actions workflow files
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "weekly"
--- a/.gitignore
+++ b/.gitignore
@ -105,9 +105,6 @@ sim/questa/wkdir
 sim/questa/ucdb
 sim/questa/cov
 sim/questa/fcov
-sim/questa/fcovrvvi
-sim/questa/fcovrvvi_logs
-sim/questa/fcovrvvi_ucdb
 sim/questa/fcov_logs
 sim/questa/fcov_ucdb
 sim/questa/riscv.ucdb
--- a/.gitmodules
+++ b/.gitmodules
@ -8,9 +8,6 @@
 [submodule "addins/coremark"]
 	path = addins/coremark
 	url = https://github.com/eembc/coremark
-[submodule "addins/FreeRTOS-Kernel"]
-	path = addins/FreeRTOS-Kernel
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
 [submodule "addins/vivado-boards"]
 	path = addins/vivado-boards
 	url = https://github.com/Digilent/vivado-boards/
--- a/8
+++ b/8
@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory

 SIM = ${WALLY}/sim

-.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
+.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean

-all: riscof	testfloat combined_IF_vectors zsbl coverage # benchmarks
+all: riscof	testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks

 # riscof builds the riscv-arch-test and wally-riscv-arch-test suites
 riscof:
@ -36,6 +36,10 @@ embench:
 coverage:
 	$(MAKE) -C tests/coverage

+cvw-arch-verif:
+	$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
+
 clean:
 	$(MAKE) clean -C sim
 	$(MAKE) clean -C ${WALLY}/tests/fp
+	$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif
--- a/README.md
+++ b/README.md
@ -196,12 +196,13 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to
 # Adding Cron Job for nightly builds

 If you want to add a cronjob you can do the following:
-1) Set up the email client `mutt` for your distribution
+1) Set up the email client `mutt` to send emails through the command line
 2) Enter `crontab -e` into a terminal
-3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
+3) add this code to test cloning CVW, making CVW's tests, then running `regression-wally --nightly --buildroot` every day at 21:30 in your local time
 ```bash
-30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
+30 21 * * * curl -L https://raw.githubusercontent.com/openhwgroup/cvw/refs/heads/main/bin/nightly_build.py | python - --path {PATH_FOR_NIGHTLY_RUNS} --target all --tests all --send_email harris@hmc.edu,rose@rosethompson.net
 ```
+This utility will take up approximately 100 GB on your hard drive. You can also run the script directly from `bin/nightly_build.py`.

 # Example wsim commands

--- a/addins/FreeRTOS-Kernel
+++ b/addins/FreeRTOS-Kernel
@ -1 +0,0 @@
-Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31
--- a/addins/cvw-arch-verif
+++ b/addins/cvw-arch-verif
@ -1 +1 @@
-Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769
+Subproject commit 812f30af765c0a692c506e42493f494278c00fe0
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@ -1 +1 @@
-Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401
+Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca
--- a/addins/verilog-ethernet
+++ b/addins/verilog-ethernet
@ -1 +1 @@
-Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d
+Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d
--- a/addins/vivado-boards
+++ b/addins/vivado-boards
@ -1 +1 @@
-Subproject commit e5f0728cd284d10080ae8eb03fc86e7b5eafcb72
+Subproject commit 8ed4f9981da1d80badb0b1f65e250b2dbf7a564d
--- a/bin/lint-wally
+++ b/bin/lint-wally
@ -30,7 +30,7 @@ for config in ${configs[@]}; do
    if !($verilator --lint-only --quiet --top-module wallywrapper \
         "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
         $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
-         -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
+         -Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
        if [ "$1" == "-nightly" ]; then
            echo -e "${RED}$config failed lint${NC}"
            fails=$((fails+1))
--- a/bin/regression-wally
+++ b/bin/regression-wally
@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode):
        for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
            for file in filenames:
                # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
-                if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1):
+                if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or 
+                    (file.endswith("ALL.elf") and fcovMode == 1)):
                    fullfile = os.path.join(dirpath, file)
                    fields = fullfile.rsplit('/', 3)
                    if (fields[2] == "ref"):
@ -419,9 +420,11 @@ if (args.ccov):  # only run RV64GC tests on Questa in code coverage mode
    addTests(tests64gc_nofp, coveragesim)
    if (args.fp):
        addTests(tests64gc_fp, coveragesim)
-elif (args.fcov):  # only run RV64GC tests on Questa in lockstep in functional coverage mode
+elif (args.fcov):  # run tests in lockstep in functional coverage mode
    addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
    addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
+    addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1)
+    addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1)
    #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)

 else: 
@ -436,6 +439,7 @@ else:
 if (args.nightly):
    addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0)
    addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0)
+    addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0)
    addTests(derivconfigtests, defaultsim)
    # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.

@ -515,7 +519,7 @@ def main():
            pass
    if args.ccov:
        TIMEOUT_DUR = 20*60 # seconds
-        os.system('rm -f questa/cov/*.ucdb')
+        os.system('rm -f questa/ucdb/* questa/cov/*')
    elif args.fcov:
        TIMEOUT_DUR = 8*60
        os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
@ -532,7 +536,7 @@ def main():
    # max out at a limited number of concurrent processes to not overwhelm the system
    # right now fcov, ccov, nightly all use Imperas
    if (args.ccov or args.fcov or args.nightly):
-        ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses
+        ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses
    else:
        ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests
    with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
@ -552,7 +556,7 @@ def main():
    if args.ccov:
        os.system('make QuestaCodeCoverage')
    if args.fcov:
-        os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
+        os.system('make -C '+WALLY+'/addins/cvw-arch-verif merge')
    # Count the number of failures
    if num_fail:
        print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
--- a/bin/wsim
+++ b/bin/wsim
@ -27,7 +27,6 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
 parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
 parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
 parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
-parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
 parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
 parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
 parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
@ -70,7 +69,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite
    exit(1)

 # Validate arguments
-if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose):
+if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose):
    if args.sim not in ["questa", "vcs"]:
        print("Option only supported for Questa and VCS")
        exit(1)
@ -88,7 +87,7 @@ if (args.tb == "testbench_fp"):
 if(int(args.locksteplog) >= 1): EnableLog = 1
 else: EnableLog = 0
 prefix = ""
-if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
+if (args.lockstep or args.lockstepverbose or args.fcov):
    if (args.sim == "questa" or args.sim == "vcs"):
        imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
        if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
@ -101,12 +100,6 @@ if (args.sim == "questa"):
 if (args.lockstep or args.lockstepverbose):
    if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
    else: ImperasPlusArgs = ""
-    if(args.fcovimp):
-        CovEnableStr = "1" if int(args.covlog) > 0  else "0"
-        if(args.covlog >= 1): EnableLog = 1
-        else: EnableLog = 0
-        ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr
-        suffix = ""
    if(args.fcov):
        CovEnableStr = "1" if int(args.covlog) > 0  else "0";
        if(args.covlog >= 1): EnableLog = 1
@ -130,8 +123,6 @@ if (args.ccov):
    flags += " --ccov"
 if (args.fcov):
    flags += " --fcov"
-if (args.fcovimp):
-    flags += " --fcovimp"

 #  create the output sub-directories.
 regressionDir = WALLY + '/sim/'
--- a/config/rv32gc/coverage.svh
+++ b/config/rv32gc/coverage.svh
@ -8,6 +8,10 @@
 // Define XLEN, used in covergroups
 `define XLEN32 1

+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 32'h0000
+`define CLINT_BASE 64'h02000000
+
 // Unprivileged extensions
 `include "RV32I_coverage.svh"
 `include "RV32M_coverage.svh"
@ -29,9 +33,15 @@
 `include "RV32ZcbZbb_coverage.svh"
 `include "RV32Zcf_coverage.svh"
 `include "RV32Zcd_coverage.svh"
+`include "RV32Zicsr_coverage.svh"

 // Privileged extensions
 `include "ZicsrM_coverage.svh"
 `include "ZicsrF_coverage.svh"
+`include "ZicsrU_coverage.svh"
 `include "RV32VM_coverage.svh"
 `include "RV32VM_PMP_coverage.svh"
+`include "EndianU_coverage.svh"
+`include "EndianM_coverage.svh"
+`include "EndianS_coverage.svh"
+`include "ExceptionsM_coverage.svh"
--- a/config/rv32gc/imperas.ic
+++ b/config/rv32gc/imperas.ic
@ -36,7 +36,7 @@
 --override cpu/Zicboz=T
 --override cmomp_bytes=64  # Zic64b
 --override cmoz_bytes=64   # Zic64b
--override lr_sc_grain=8   # Za64rs requires <=64; we use native word size
+--override lr_sc_grain=4   # Za64rs requires <=64; we use native word size

 # 64 KiB continuous huge pages supported
 #--override cpu/Svpbmt=F
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@ -8,6 +8,10 @@
 // Define XLEN, used in covergroups
 `define XLEN64 1

+// Define relevant addresses
+`define ACCESS_FAULT_ADDRESS 64'h00000000
+`define CLINT_BASE 64'h02000000
+
 // Unprivileged extensions
 `include "RV64I_coverage.svh"
 `include "RV64M_coverage.svh"
@ -29,11 +33,17 @@
 `include "RV64ZcbZbb_coverage.svh"
 `include "RV64ZcbZba_coverage.svh"
 `include "RV64Zcd_coverage.svh"
+`include "RV64Zicsr_coverage.svh"

 // Privileged extensions
 `include "RV64VM_coverage.svh"
 `include "ZicsrM_coverage.svh"
 `include "ZicsrF_coverage.svh"
+`include "ZicsrU_coverage.svh"
+`include "EndianU_coverage.svh"
+`include "EndianM_coverage.svh"
+`include "EndianS_coverage.svh"
+`include "ExceptionsM_coverage.svh"
 // `include "RV64VM_PMP_coverage.svh"
 // `include "RV64CBO_VM_coverage.svh"
 // `include "RV64CBO_PMP_coverage.svh"
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@ -122,9 +122,3 @@ localparam FMALEN = 3*NF + 6;
 localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));

 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
-
-// Disable spurious Verilator warnings
-
-/* verilator lint_off STMTDLY */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@ -95,11 +95,7 @@ localparam cvw_t P = '{
  PLIC_SPI_ID :        PLIC_SPI_ID,
  PLIC_SDC_ID :        PLIC_SDC_ID,
  BPRED_SUPPORTED :        BPRED_SUPPORTED,
-                       /* verilator lint_off ENUMVALUE */
-                       // *** definitely need to fix this.
-                       // it thinks we are casting from the enum type to BPRED_TYPE.
  BPRED_TYPE :        BPRED_TYPE,
-                       /* verilator lint_on ENUMVALUE */
  BPRED_SIZE :        BPRED_SIZE,
  BPRED_NUM_LHR : BPRED_NUM_LHR,                       
  BTB_SIZE :        BTB_SIZE,
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@ -103,26 +103,6 @@ if {[lcheck lst "--ccov"]} {
    set CoverageVsimArg "-coverage"
 }

-# if --fcovimp found set flag and remove from list
-if {[lcheck lst "--fcovimp"]} {
-    set FunctCoverage 1
-    set FCvlog "+define+INCLUDE_TRACE2COV \
-                +define+IDV_INCLUDE_TRACE2COV \
-                +define+COVER_BASE_RV64I \
-                +define+COVER_LEVEL_DV_PR_EXT \
-                +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source"
-    set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
-    # Uncomment various cover statements below to control which extensions get functional coverage
-    lappend FCdefineCOVER_EXTS "+define+COVER_RV64I"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64M"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64A"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64F"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64D"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR"
-    #lappend FCdefineCOVER_EXTS "+define+COVER_RV64C"
-
-}
-
 # if --fcov found set flag and remove from list
 if {[lcheck lst "--fcov"]} {
    set FunctCoverage 1
--- a/site-setup.csh
+++ b/site-setup.csh
@ -49,7 +49,7 @@ setenv SPIKE_PATH $RISCV/bin										# Change this for your path to riscv-isa-s
 setenv IDV $RISCV/ImperasDV-OpenHW
 if ($?IDV) then
    # echo "Imperas exists"
-    setenv IMPERAS_HOME $IDV/Imperas
+    setenv IMPERAS_HOME $IDV
    setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC
    setenv ROOTDIR ~/
    source ${IMPERAS_HOME}/bin/setup.sh
--- a/site-setup.sh
+++ b/site-setup.sh
@ -66,7 +66,7 @@ export SPIKE_PATH=$RISCV/bin										# Copy this as it is
 export IDV=$RISCV/ImperasDV-OpenHW
 if [ -e "$IDV" ]; then
    # echo "Imperas exists"
-    export IMPERAS_HOME=$IDV/Imperas
+    export IMPERAS_HOME=$IDV
    export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
    export ROOTDIR=~/
    source "${IMPERAS_HOME}"/bin/setup.sh
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////

 module cache import cvw::*; #(parameter cvw_t P,
-                              parameter PA_BITS, XLEN, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+                              parameter PA_BITS, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
  input  logic                   clk,
  input  logic                   reset,
  input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@ -66,11 +66,7 @@ module cache import cvw::*; #(parameter cvw_t P,
  localparam                     SETLEN = $clog2(NUMSETS);          // Number of set bits
  localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
  localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
-  localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
-  localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
  localparam                     FLUSHADRTHRESHOLD = NUMSETS - 1;   // Used to determine when flush is complete
-  localparam                     LOGLLENBYTES = $clog2(WORDLEN/8);   // Number of bits to address a word
-

  logic                          SelAdrData;
  logic                          SelAdrTag;
@ -122,14 +118,14 @@ module cache import cvw::*; #(parameter cvw_t P,
    AdrSelMuxSelLRU, CacheSetLRU);

  // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
+  cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
    .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
    .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);

  // Select victim way for associative caches
  if(NUMWAYS > 1) begin:vict
-    cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
+    cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU(
      .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
  end else 
@ -172,11 +168,7 @@ module cache import cvw::*; #(parameter cvw_t P,
  if(!READ_ONLY_CACHE) begin:WriteSelLogic
    logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;

-    // Adjust byte mask from word to cache line
-
-    localparam                     CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
-    localparam                     LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
-    
+    // Adjust byte mask from word to cache line    
    logic [LINELEN/8-1:0]          BlankByteMask;
    assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
    assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0;
@ -231,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P,
  // Cache FSM
  /////////////////////////////////////////////////////////////////////////////////////////////
  
-  cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
+  cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
    .FlushStage, .CacheRW, .Stall,
    .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, 
    .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////

 module cacheLRU
-  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) (
+  #(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) (
  input  logic                clk, 
  input  logic                reset,
  input  logic                FlushStage,
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@ -28,8 +28,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////

-module cachefsm import cvw::*; #(parameter cvw_t P,
-                                 parameter READ_ONLY_CACHE = 0) (
+module cachefsm #(parameter READ_ONLY_CACHE = 0) (
  input  logic       clk,
  input  logic       reset,
  // hazard and privilege unit
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////

 module cacheway import cvw::*; #(parameter cvw_t P, 
-                  parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
+                  parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
                  OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
  input  logic                        clk,
  input  logic                        reset,
@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
  output logic                        DirtyWay   ,    // The selected way is dirty
  output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid

-  localparam                          WORDSPERLINE = LINELEN/XLEN;
-  localparam                          BYTESPERLINE = LINELEN/8;
-  localparam                          LOGWPL = $clog2(WORDSPERLINE);
-  localparam                          LOGXLENBYTES = $clog2(XLEN/8);
-  localparam                          BYTESPERWORD = XLEN/8;
-
  logic [NUMSETS-1:0]                ValidBits;
  logic [NUMSETS-1:0]                DirtyBits;
  logic [LINELEN-1:0]                 ReadDataLine;
@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,

  localparam           NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
  localparam           SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
-  localparam           LOGNUMSRAM = $clog2(NUMSRAM);
  
  for(words = 0; words < NUMSRAM; words++) begin: word
    if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@ -38,7 +38,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
  output logic [P.DIVb+3:0] FirstWS, FirstWC       // Q4.DIVb
 );

-  /* verilator lint_off UNOPTFLAT */
  logic [P.DIVb+3:0]      WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb
  logic [P.DIVb+3:0]      WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
  logic [P.DIVb+3:0]      WS[P.DIVCOPIES:0];       // Q4.DIVb
@ -56,7 +55,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
  logic [P.DIVb+1:0]      NextC;                   // Q2.DIVb
  logic [P.DIVb:0]        UMux, UMMux;             // U1.DIVb
  logic [P.DIVb:0]        initU, initUM;           // U1.DIVb
-  /* verilator lint_on UNOPTFLAT */

  // Top Muxes and Registers
  // When start is asserted, the inputs are loaded into the divider.
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@ -136,7 +136,7 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
    // calculate right shift amount RightShiftX to complete in discrete number of steps
    if (P.RK > 1) begin // more than 1 bit per cycle
      logic [$clog2(P.RK)-1:0] RightShiftX;
-      /* verilator lint_offf WIDTH */
+      /* verilator lint_off WIDTH */
      assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
      assign DivXShifted = DivX >> RightShiftX;                     // shift X by up to R*K-1 to complete in n steps
      /* verilator lint_on WIDTH */
--- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@ -28,7 +28,6 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////


-/* verilator lint_off UNOPTFLAT */
 module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
  input  logic [P.DIVb+3:0] D, DBar,        // Q4.DIVb
  input  logic [P.DIVb:0]   U, UM,          // U1.DIVb
@ -40,7 +39,6 @@ module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
  output logic [P.DIVb:0]   UNext, UMNext,  // U1.DIVb
  output logic [P.DIVb+3:0] WSNext, WCNext  // Q4.DIVb
 );
- /* verilator lint_on UNOPTFLAT */

  logic [P.DIVb+3:0]        Dsel;     // Q4.DIVb
  logic                     up, uz;
--- a/src/fpu/fround.sv
+++ b/src/fpu/fround.sv
@ -115,9 +115,9 @@ module fround import cvw::*;  #(parameter cvw_t P) (
  ///////////////////////////

  // Exact logic
-  // verilator lint_off WIDTHEXPAND
+  /* verilator lint_off WIDTHEXPAND */
  assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf.  Also check that Xe is positive to avoid wraparound problems
-  // verilator lint_on WIDTHEXPAND
+  /* verilator lint_on WIDTHEXPAND */

  // Rounding logic: determine whether to round up in magnitude
  always_comb begin
--- a/src/generic/prioritythermometer.sv
+++ b/src/generic/prioritythermometer.sv
@ -39,11 +39,9 @@ module prioritythermometer #(parameter N = 8) (
  //  Rather than linear.

  // create thermometer code mask
-  /* verilator lint_off UNOPTFLAT */
  genvar i;
  assign y[0] = ~a[0];
  for (i=1; i<N; i++) begin:therm
    assign y[i] = y[i-1] & ~a[i];
  end
-  /* verilator lint_on UNOPTFLAT */
 endmodule
--- a/src/hazard/hazard.sv
+++ b/src/hazard/hazard.sv
@ -27,7 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////

-module hazard import cvw::*;  #(parameter cvw_t P) ( 
+module hazard ( 
  input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
  input  logic  StructuralStallD,
  input  logic  LSUStallM, IFUStallF,
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@ -236,7 +236,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
      
      assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
      assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS),
              .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
              .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
      icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@ -121,11 +121,9 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
  logic                  DCacheCommittedM;                       // D$ memory operation started, delay interrupts

  logic [P.LLEN-1:0]     DTIMReadDataWordM;                      // DTIM read data
-  /* verilator lint_off WIDTHEXPAND */  
  logic [MLEN-1:0]       DCacheReadDataWordM;                    // D$ read data
  logic [MLEN-1:0]       LSUWriteDataSpillM;                     // Final write data
  logic [MLEN/8-1:0]     ByteMaskSpillM;                         // Selects which bytes within a word to write
-  /* verilator lint_on WIDTHEXPAND */
  logic [P.LLEN-1:0]     DCacheReadDataWordSpillM;               // D$ read data
  logic [P.LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
  logic [P.LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
@ -326,7 +324,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
      assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
      assign FlushDCache = FlushDCacheM & ~(SelHPTW);
      
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
              .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
        .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
        .CacheRW(CacheRWM), 
--- a/src/mdu/divstep.sv
+++ b/src/mdu/divstep.sv
@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////

-/* verilator lint_off UNOPTFLAT */
-
 module divstep #(parameter XLEN) (
  input  logic [XLEN-1:0] W,     // Residual in
  input  logic [XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
@ -46,5 +44,3 @@ module divstep #(parameter XLEN) (
  assign qi = ~qib;
  mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
 endmodule
-
-/* verilator lint_on UNOPTFLAT */
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@ -88,6 +88,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
  // .. up to 15 more at consecutive addresses
  localparam PMPADDR0      = 12'h3B0;
  // ... up to 63 more at consecutive addresses
+  /* verilator lint_off UNUSEDPARAM */
  localparam TSELECT       = 12'h7A0;
  localparam TDATA1        = 12'h7A1;
  localparam TDATA2        = 12'h7A2;
@ -96,6 +97,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
  localparam DPC           = 12'h7B1;
  localparam DSCRATCH0     = 12'h7B2;
  localparam DSCRATCH1     = 12'h7B3;
+  /* verilator lint_off UNUSEDPARAM */
  // Constants
  localparam ZERO = {(P.XLEN){1'b0}};
  // when compressed instructions are supported, there can't be misaligned instructions
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@ -67,8 +67,6 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
  localparam STIMECMPH  = 12'h15D;
  localparam SATP       = 12'h180;
  // Constants
-  localparam ZERO         = {(P.XLEN){1'b0}};
-  localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);

  logic                    WriteSTVECM;
  logic                    WriteSSCRATCHM, WriteSEPCM;
--- a/src/uncore/clint_apb.sv
+++ b/src/uncore/clint_apb.sv
@ -115,7 +115,7 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
    always_ff @(posedge PCLK) 
      if (~PRESETn) begin
        MSIP <= 1'b0;
-        MTIMECMP <= '0;
+        MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
      end else if (memwrite) begin
        if (entry == 16'h0000) MSIP <= PWDATA[0];
        if (entry == 16'h4000) 
--- a/src/uncore/ram_ahb.sv
+++ b/src/uncore/ram_ahb.sv
@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////

 module ram_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
+                                 parameter RANGE = 65535, PRELOAD = 0) (
  input  logic                 HCLK, HRESETn, 
  input  logic                 HSELRam,
  input  logic [P.PA_BITS-1:0] HADDR,
--- a/src/uncore/rom_ahb.sv
+++ b/src/uncore/rom_ahb.sv
@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////

 module rom_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
+                                 parameter RANGE = 65535, PRELOAD = 0) (
  input  logic                 HCLK, HRESETn, 
  input  logic                 HSELRom,
  input  logic [P.PA_BITS-1:0] HADDR,
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@ -114,7 +114,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
  
  /* verilator lint_off UNDRIVEN */
  logic [2:0]  TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
-  /* verilator lint_off UNDRIVEN */
+  /* verilator lint_on UNDRIVEN */
  logic [7:0]  ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)

  // Shift reg signals
@ -184,7 +184,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
        case(Entry)
          SPI_TXDATA:  if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
        endcase
-      /* verilator lint_off CASEINCOMPLETE */
+      /* verilator lint_on CASEINCOMPLETE */
      
      // According to FU540 spec: Once interrupt is pending, it will remain set until number 
      // of entries in tx/rx fifo is strictly more/less than tx/rxmark
--- a/src/uncore/uartPC16550D.sv
+++ b/src/uncore/uartPC16550D.sv
@ -335,10 +335,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
    end

  assign rxfifoempty = (rxfifohead == rxfifotail);
-  // verilator lint_off WIDTH
+  /* verilator lint_off WIDTH */
  assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : 
                         (rxfifohead + 16 - rxfifotail);
-  // verilator lint_on WIDTH
+  /* verilator lint_on WIDTH */
  assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
  assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet
  //assign rxfifotimeout = 0; // disabled pending fix
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@ -109,13 +109,13 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
                
  // on-chip RAM
  if (P.UNCORE_RAM_SUPPORTED) begin : ram
-    ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
+    ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
      .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
      .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
  end else assign {HREADRam, HRESPRam, HREADYRam} = '0;

 if (P.BOOTROM_SUPPORTED) begin : bootrom
-    rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
+    rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
    bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
      .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
  end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@ -271,7 +271,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
  end

  // global stall and flush control  
-  hazard #(P) hzu(
+  hazard hzu(
    .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
    .StructuralStallD,
    .LSUStallM, .IFUStallF,
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@ -35,37 +35,36 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
  
  // wally specific signals
-  logic 						 reset;
-  logic 						 clk;
-  logic                          InstrValidD, InstrValidE;
-  logic                          StallF, StallD;
-  logic                          STATUS_SXL, STATUS_UXL;
-  logic [P.XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
-  logic [31:0]      			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
-  logic 						 InstrValidM, InstrValidW;
-  logic 						 StallE, StallM, StallW;
-  logic 						 FlushD, FlushE, FlushM, FlushW;
-  logic 						 TrapM, TrapW;
-  logic 						 HaltM, HaltW;
-  logic [1:0] 					 PrivilegeModeW;
-  logic [P.XLEN-1:0] 			 rf[NUMREGS];
-  logic [NUMREGS-1:0] 			 rf_wb;
-  logic [4:0] 					 rf_a3;
-  logic 						 rf_we3;
-  logic [P.FLEN-1:0] 			 frf[32];
-  logic [`NUM_REGS-1:0] 		 frf_wb;
-  logic [4:0] 					 frf_a4;
-  logic 						 frf_we4;
-  logic [P.XLEN-1:0]              CSRArray [4095:0];
-  logic [P.XLEN-1:0] 			 CSRArrayOld [4095:0];
-  logic [`NUM_CSRS-1:0] 		 CSR_W;
-  logic 						 CSRWriteM, CSRWriteW;
-  logic [11:0] 					 CSRAdrM, CSRAdrW;
-  logic                          wfiM;
-  logic                          InterruptM, InterruptW;
+  logic                  reset;
+  logic                  clk;
+  logic                  InstrValidD, InstrValidE;
+  logic                  StallF, StallD;
+  logic                  STATUS_SXL, STATUS_UXL;
+  logic [P.XLEN-1:0]     PCNextF, PCF, PCD, PCE, PCM, PCW;
+  logic [31:0]           InstrRawD, InstrRawE, InstrRawM, InstrRawW;
+  logic                  InstrValidM, InstrValidW;
+  logic                  StallE, StallM, StallW;
+  logic                  FlushD, FlushE, FlushM, FlushW;
+  logic                  TrapM, TrapW;
+  logic                  HaltM, HaltW;
+  logic [1:0]            PrivilegeModeW;
+  logic [P.XLEN-1:0]     rf[NUMREGS];
+  logic [NUMREGS-1:0]    rf_wb;
+  logic [4:0]            rf_a3;
+  logic                  rf_we3;
+  logic [P.FLEN-1:0]     frf[32];
+  logic [`NUM_REGS-1:0]  frf_wb;
+  logic [4:0]            frf_a4;
+  logic                  frf_we4;
+  logic [P.XLEN-1:0]     CSRArray [4095:0];
+  logic [P.XLEN-1:0]     CSRArrayOld [4095:0];
+  logic [`NUM_CSRS-1:0]  CSR_W;
+  logic                  CSRWriteM, CSRWriteW;
+  logic [11:0]           CSRAdrM, CSRAdrW;
+  logic                  wfiM;
+  logic                  InterruptM, InterruptW;

  //For VM Verification
-
  logic [(P.XLEN-1):0]     VAdrIM,VAdrDM,VAdrIW,VAdrDW;
  logic [(P.XLEN-1):0]     PTE_iM,PTE_dM,PTE_iW,PTE_dW;
  logic [(P.PA_BITS-1):0]  PAIM,PADM,PAIW,PADW;
@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
  logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;

-    
  assign clk = testbench.dut.clk;
  //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
  assign InstrValidD    = testbench.dut.core.ieu.c.InstrValidD;
@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  assign wfiM           = testbench.dut.core.priv.priv.wfiM;
  assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;

-  //FOr VM Verification
+  //For VM Verification
  assign VAdrIM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
  assign VAdrDM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
  assign PAIM           = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
@ -116,25 +114,22 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
  assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 

-  
-
  logic valid;
-  int csrid;
-
+  
  always_comb begin
-	// Since we are detected the CSR change by comparing the old value we need to
-	// ensure the CSR is detected when the pipeline's Writeback stage is not
-	// stalled.  If it is stalled we want CSRArray to hold the old value.
-	if(valid) begin 
-	  // machine CSRs
-	  // *** missing PMP and performance counters.
-	
-      // PMPCFG  space is 0-15 3a0 - 3af
-	  int i, i4, i8, csrid;
+    // Since we are detected the CSR change by comparing the old value we need to
+    // ensure the CSR is detected when the pipeline's Writeback stage is not
+    // stalled.  If it is stalled we want CSRArray to hold the old value.
+    if(valid) begin 
+      // PMPCFG CSRs (space is 0-15 3a0 - 3af)
+      localparam inc = P.XLEN == 32 ? 4 : 8;
+      int i, i4, i8, csrid;
      logic [P.XLEN-1:0] pmp;
-      for (i=0; i<P.PMP_ENTRIES; i+=8) begin
+
+      for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
        i4 = i / 4;
-        i8 = (i / 8) * 8;
+        i8 = (i / inc) * inc;
+        csrid = 12'h3A0 + i4;
        pmp = 0;
        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
@ -145,143 +140,183 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
        pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
        
-        csrid = 12'h3A0 + i4;
        CSRArray[csrid] = pmp;
      end

-      // PMPADDR space is 0-63 3b0 - 3ef
+      // PMPADDR CSRs (space is 0-63 3b0 - 3ef)
      for (i=0; i<P.PMP_ENTRIES; i++) begin
+        csrid = 12'h3B0 + i;;
        pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
-        
-        csrid = 12'h3B0 + i;
        CSRArray[csrid] = pmp;
      end
-      
-	  CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
-	  CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW;
-	  CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
-	  CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
-	  CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
-	  CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
-	  CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
-	  CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-	  CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
-	  CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
-	  CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
-	  CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
-	  CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
-	  CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
-	  CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
-	  CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
-	  CSRArray[12'hF11] = 0;
-	  CSRArray[12'hF12] = 0;
-	  CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
-	  CSRArray[12'hF15] = 0;
-	  CSRArray[12'h34A] = 0;
-	  // MCYCLE and MINSTRET
-	  CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
-	  CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-	  // supervisor CSRs
-	  CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
-	  CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
-	  CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
-	  CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
-	  CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
-	  CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
-	  CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
-	  CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
-	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
-	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
-	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
-	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
-	  // user CSRs
-	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
-	  CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
-	  CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
-	
-    if (P.XLEN == 32) begin
-      CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
-      CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
-      CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
-    end
-	end else begin // hold the old value if the pipeline is stalled.

+      // M-mode trap CSRs
+      CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
+      CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
+      CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+      CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
+      CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
+      CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
+      CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
+      CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
+      CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
+      CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
+      
+      // S-mode trap CSRs
+      CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
+      CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
+      CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
+      CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
+      CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
+      CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
+      CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
+      CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+
+      // Virtual Memory CSRs
+      CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
+
+      // Floating-Point CSRs
+      CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
+      CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
+      CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
+
+      // Counters / Performance Monitoring CSRs
+      CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
+      CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
+      CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
+      // mhpmevent3-31 not connected (232-33F)
+      CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
+      CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
+      // mhpmcounter3-31 not connected (B03-B1F)
+      // cycle, time, instret not connected (C00-C02)
+      // hpmcounter3-31 not connected (C03-C1F)
+
+      // Machine Information Registers and Configuration CSRs
+      CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
+      CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
+      CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
+      CSRArray[12'h747] = 0; // mseccfg
+      CSRArray[12'hF11] = 0; //mvendorid
+      CSRArray[12'hF12] = 0; // marchid
+      CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
+      CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
+      CSRArray[12'hF15] = 0; //mconfigptr
+
+      // Sstc CSRs
+      CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
+      
+      // Zkr CSRs
+      // seed not connected (015)
+
+      // extra CSRs for RV32
+      if (P.XLEN == 32) begin
+        CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
+        CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
+        CSRArray[12'h757] = 0; // mseccfgh
+        CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
+      end
+    end else begin // hold the old value if the pipeline is stalled.
      // PMP CFG 3A0 to 3AF
+      int csrid;
      for(csrid='h3A0; csrid<='h3AF; csrid++)
-          CSRArray[csrid] = CSRArrayOld[csrid];
+        CSRArray[csrid] = CSRArrayOld[csrid];
      
      // PMP ADDR 3B0 to 3EF
      for(csrid='h3B0; csrid<='h3EF; csrid++)
-          CSRArray[csrid] = CSRArrayOld[csrid];
+        CSRArray[csrid] = CSRArrayOld[csrid];

-	  CSRArray[12'h300] = CSRArrayOld[12'h300];
-	  CSRArray[12'h310] = CSRArrayOld[12'h310];
-	  CSRArray[12'h305] = CSRArrayOld[12'h305];
-	  CSRArray[12'h341] = CSRArrayOld[12'h341];
-	  CSRArray[12'h306] = CSRArrayOld[12'h306];
-	  CSRArray[12'h320] = CSRArrayOld[12'h320];
-	  CSRArray[12'h302] = CSRArrayOld[12'h302];
-	  CSRArray[12'h303] = CSRArrayOld[12'h303];
-	  CSRArray[12'h344] = CSRArrayOld[12'h344];
-	  CSRArray[12'h304] = CSRArrayOld[12'h304];
-	  CSRArray[12'h301] = CSRArrayOld[12'h301];
-	  CSRArray[12'h30A] = CSRArrayOld[12'h30A];
-	  CSRArray[12'hF14] = CSRArrayOld[12'hF14];
-	  CSRArray[12'h340] = CSRArrayOld[12'h340];
-	  CSRArray[12'h342] = CSRArrayOld[12'h342];
-	  CSRArray[12'h343] = CSRArrayOld[12'h343];
-	  CSRArray[12'hF11] = CSRArrayOld[12'hF11];
-	  CSRArray[12'hF12] = CSRArrayOld[12'hF12];
-	  CSRArray[12'hF13] = CSRArrayOld[12'hF13];
-	  CSRArray[12'hF15] = CSRArrayOld[12'hF15];
-	  CSRArray[12'h34A] = CSRArrayOld[12'h34A];
-	  // MCYCLE and MINSTRET
-	  CSRArray[12'hB00] = CSRArrayOld[12'hB00];
-	  CSRArray[12'hB02] = CSRArrayOld[12'hB02];
-	  // supervisor CSRs
-	  CSRArray[12'h100] = CSRArrayOld[12'h100];
-	  CSRArray[12'h104] = CSRArrayOld[12'h104];
-	  CSRArray[12'h105] = CSRArrayOld[12'h105];
-	  CSRArray[12'h141] = CSRArrayOld[12'h141];
-	  CSRArray[12'h106] = CSRArrayOld[12'h106];
-	  CSRArray[12'h10A] = CSRArrayOld[12'h10A];
-	  CSRArray[12'h180] = CSRArrayOld[12'h180];
-	  CSRArray[12'h140] = CSRArrayOld[12'h140];
-	  CSRArray[12'h143] = CSRArrayOld[12'h143];
-	  CSRArray[12'h142] = CSRArrayOld[12'h142];
-	  CSRArray[12'h144] = CSRArrayOld[12'h144];
-	  CSRArray[12'h14D] = CSRArrayOld[12'h14D];
-	  // user CSRs
-	  CSRArray[12'h001] = CSRArrayOld[12'h001];
-	  CSRArray[12'h002] = CSRArrayOld[12'h002];
-	  CSRArray[12'h003] = CSRArrayOld[12'h003];
-	end	  
+      // M-mode trap CSRs
+      CSRArray[12'h300] = CSRArrayOld[12'h300];
+      CSRArray[12'h302] = CSRArrayOld[12'h302];
+      CSRArray[12'h303] = CSRArrayOld[12'h303];
+      CSRArray[12'h304] = CSRArrayOld[12'h304];
+      CSRArray[12'h305] = CSRArrayOld[12'h305];
+      CSRArray[12'h340] = CSRArrayOld[12'h340];
+      CSRArray[12'h341] = CSRArrayOld[12'h341];
+      CSRArray[12'h342] = CSRArrayOld[12'h342];
+      CSRArray[12'h343] = CSRArrayOld[12'h343];
+      CSRArray[12'h344] = CSRArrayOld[12'h344];
+
+      // S-mode trap CSRs
+      CSRArray[12'h100] = CSRArrayOld[12'h100];
+      CSRArray[12'h104] = CSRArrayOld[12'h104];
+      CSRArray[12'h105] = CSRArrayOld[12'h105];
+      CSRArray[12'h140] = CSRArrayOld[12'h140];
+      CSRArray[12'h141] = CSRArrayOld[12'h141];
+      CSRArray[12'h142] = CSRArrayOld[12'h142];
+      CSRArray[12'h143] = CSRArrayOld[12'h143];
+      CSRArray[12'h144] = CSRArrayOld[12'h144];
+
+      // Virtual Memory CSRs
+      CSRArray[12'h180] = CSRArrayOld[12'h180] ;
+
+      // Floating-Point CSRs
+      CSRArray[12'h001] = CSRArrayOld[12'h001];
+      CSRArray[12'h002] = CSRArrayOld[12'h002];
+      CSRArray[12'h003] = CSRArrayOld[12'h003];
+
+      // Counters / Performance Monitoring CSRs
+      CSRArray[12'h306] = CSRArrayOld[12'h306];
+      CSRArray[12'h106] = CSRArrayOld[12'h106];
+      CSRArray[12'h320] = CSRArrayOld[12'h320];
+      // mhpmevent3-31 not connected (232-33F)
+      CSRArray[12'hB00] = CSRArrayOld[12'hB00];
+      CSRArray[12'hB02] = CSRArrayOld[12'hB02];
+      // mhpmcounter3-31 not connected (B03-B1F)
+      // cycle, time, instret not connected (C00-C02)
+      // hpmcounter3-31 not connected (C03-C1F)
+
+      // Machine Information Registers and Configuration CSRs
+      CSRArray[12'h301] = CSRArrayOld[12'h301];
+      CSRArray[12'h30A] = CSRArrayOld[12'h30A];
+      CSRArray[12'h10A] = CSRArrayOld[12'h10A];
+      CSRArray[12'h747] = CSRArrayOld[12'h747];
+      CSRArray[12'hF11] = CSRArrayOld[12'hF11];
+      CSRArray[12'hF12] = CSRArrayOld[12'hF12];
+      CSRArray[12'hF13] = CSRArrayOld[12'hF13];
+      CSRArray[12'hF14] = CSRArrayOld[12'hF14];
+      CSRArray[12'hF15] = CSRArrayOld[12'hF15];
+
+      // Sstc CSRs
+      CSRArray[12'h14D] = CSRArrayOld[12'h14D];
+      
+      // Zkr CSRs
+      // seed not connected (015)
+
+      // extra CSRs for RV32
+      if (P.XLEN == 32) begin
+        CSRArray[12'h310] = CSRArrayOld[12'h310];
+        CSRArray[12'h31A] = CSRArrayOld[12'h31A];
+        CSRArray[12'h757] = CSRArrayOld[12'h757];
+        CSRArray[12'h15D] = CSRArrayOld[12'h15D];
+      end
+    end    
  end

  genvar index;
  assign rf[0] = 0;
  for(index = 1; index < NUMREGS; index += 1) 
-	assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
+  assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];

  assign rf_a3  = testbench.dut.core.ieu.dp.regf.a3;
  assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
  
  always_comb begin
-	rf_wb <= 0;
-	if(rf_we3)
-	  rf_wb[rf_a3] <= 1'b1;
+    rf_wb <= 0;
+    if(rf_we3)
+      rf_wb[rf_a3] <= 1'b1;
  end

  for(index = 0; index < NUMREGS; index += 1) 
-	assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
+  assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
  
  assign frf_a4  = testbench.dut.core.fpu.fpu.fregfile.a4;
  assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
  
  always_comb begin
-	frf_wb <= 0;
-	if(frf_we4)
-	  frf_wb[frf_a4] <= 1'b1;
+    frf_wb <= 0;
+    if(frf_we4)
+      frf_wb[frf_a4] <= 1'b1;
  end

  assign CSRAdrM  = testbench.dut.core.priv.priv.csr.CSRAdrM;
@ -290,9 +325,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  // pipeline to writeback stage
  flopenrc #(32)    InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
  flopenrc #(32)    InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(32)    InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(P.XLEN)PCWReg       (clk, reset, FlushW, ~StallW, PCM, PCW);
-  flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
+  flopenrc #(32)    InstrRawWReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrRawM, InstrRawW);
+  flopenrc #(P.XLEN)PCWReg       (clk, reset, FlushW & ~TrapM, ~StallW, PCM, PCW);
+  flopenrc #(1)     InstrValidMReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrValidM, InstrValidW);
  flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
  flopenrc #(1)     InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
  flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
@ -311,6 +346,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
+  // *** what is this used for?
  flopenrc #(1)  ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
  flopenrc #(1)  ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
  flopenrc #(1)  ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
@ -330,191 +366,302 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
  assign rvvi.intr[0][0]     = InterruptW;
  assign rvvi.mode[0][0]     = PrivilegeModeW;
  assign rvvi.ixl[0][0]      = PrivilegeModeW == 2'b11 ? 2'b10 :
-					           PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
+                               PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
  assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM :
-						       ~FlushM ? PCE :
-						       ~FlushE ? PCD :
-						       ~FlushD ? PCF : PCNextF;
+                               ~FlushM ? PCE :
+                               ~FlushE ? PCD :
+                               ~FlushD ? PCF : PCNextF;

  for(index = 0; index < `NUM_REGS; index += 1) begin
-	assign rvvi.x_wdata[0][0][index] = rf[index];
-	assign rvvi.x_wb[0][0][index]    = rf_wb[index];
-	assign rvvi.f_wdata[0][0][index] = frf[index];
-	assign rvvi.f_wb[0][0][index]    = frf_wb[index];
+    assign rvvi.x_wdata[0][0][index] = rf[index];
+    assign rvvi.x_wb[0][0][index]    = rf_wb[index];
+    assign rvvi.f_wdata[0][0][index] = frf[index];
+    assign rvvi.f_wb[0][0][index]    = frf_wb[index];
  end

  // record previous csr value.
  integer index4;
  always_ff @(posedge clk) begin
+    int csrid;
+    // PMP CFG 3A0 to 3AF
+    for(csrid='h3A0; csrid<='h3AF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+    
+    // PMP ADDR 3B0 to 3EF
+    for(csrid='h3B0; csrid<='h3EF; csrid++)
+      CSRArrayOld[csrid] = CSRArray[csrid];
+
+    // M-mode trap CSRs
    CSRArrayOld[12'h300] = CSRArray[12'h300];
-    CSRArrayOld[12'h310] = CSRArray[12'h310];
-    CSRArrayOld[12'h305] = CSRArray[12'h305];
-    CSRArrayOld[12'h341] = CSRArray[12'h341];
-    CSRArrayOld[12'h306] = CSRArray[12'h306];
-    CSRArrayOld[12'h320] = CSRArray[12'h320];
    CSRArrayOld[12'h302] = CSRArray[12'h302];
    CSRArrayOld[12'h303] = CSRArray[12'h303];
-    CSRArrayOld[12'h344] = CSRArray[12'h344];
    CSRArrayOld[12'h304] = CSRArray[12'h304];
-    CSRArrayOld[12'h301] = CSRArray[12'h301];
-    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
-    CSRArrayOld[12'hF14] = CSRArray[12'hF14];
+    CSRArrayOld[12'h305] = CSRArray[12'h305];
    CSRArrayOld[12'h340] = CSRArray[12'h340];
+    CSRArrayOld[12'h341] = CSRArray[12'h341];
    CSRArrayOld[12'h342] = CSRArray[12'h342];
    CSRArrayOld[12'h343] = CSRArray[12'h343];
-    CSRArrayOld[12'hF11] = CSRArray[12'hF11];
-    CSRArrayOld[12'hF12] = CSRArray[12'hF12];
-    CSRArrayOld[12'hF13] = CSRArray[12'hF13];
-    CSRArrayOld[12'hF15] = CSRArray[12'hF15];
-    CSRArrayOld[12'h34A] = CSRArray[12'h34A];
-    // MCYCLE and MINSTRET
-    CSRArrayOld[12'hB00] = CSRArray[12'hB00];
-    CSRArrayOld[12'hB02] = CSRArray[12'hB02];
-    // supervisor CSRs
+    CSRArrayOld[12'h344] = CSRArray[12'h344];
+
+    // S-mode trap CSRs
    CSRArrayOld[12'h100] = CSRArray[12'h100];
    CSRArrayOld[12'h104] = CSRArray[12'h104];
    CSRArrayOld[12'h105] = CSRArray[12'h105];
-    CSRArrayOld[12'h141] = CSRArray[12'h141];
-    CSRArrayOld[12'h106] = CSRArray[12'h106];
-    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
-    CSRArrayOld[12'h180] = CSRArray[12'h180];
    CSRArrayOld[12'h140] = CSRArray[12'h140];
-    CSRArrayOld[12'h143] = CSRArray[12'h143];
+    CSRArrayOld[12'h141] = CSRArray[12'h141];
    CSRArrayOld[12'h142] = CSRArray[12'h142];
+    CSRArrayOld[12'h143] = CSRArray[12'h143];
    CSRArrayOld[12'h144] = CSRArray[12'h144];
-    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
-    // user CSRs
+
+    // Virtual Memory CSRs
+    CSRArrayOld[12'h180] = CSRArray[12'h180] ;
+
+    // Floating-Point CSRs
    CSRArrayOld[12'h001] = CSRArray[12'h001];
    CSRArrayOld[12'h002] = CSRArray[12'h002];
    CSRArrayOld[12'h003] = CSRArray[12'h003];
+
+    // Counters / Performance Monitoring CSRs
+    CSRArrayOld[12'h306] = CSRArray[12'h306];
+    CSRArrayOld[12'h106] = CSRArray[12'h106];
+    CSRArrayOld[12'h320] = CSRArray[12'h320];
+    // mhpmevent3-31 not connected (232-33F)
+    CSRArrayOld[12'hB00] = CSRArray[12'hB00];
+    CSRArrayOld[12'hB02] = CSRArray[12'hB02];
+    // mhpmcounter3-31 not connected (B03-B1F)
+    // cycle, time, instret not connected (C00-C02)
+    // hpmcounter3-31 not connected (C03-C1F)
+
+    // Machine Information Registers and Configuration CSRs
+    CSRArrayOld[12'h301] = CSRArray[12'h301];
+    CSRArrayOld[12'h30A] = CSRArray[12'h30A];
+    CSRArrayOld[12'h10A] = CSRArray[12'h10A];
+    CSRArrayOld[12'h747] = CSRArray[12'h747];
+    CSRArrayOld[12'hF11] = CSRArray[12'hF11];
+    CSRArrayOld[12'hF12] = CSRArray[12'hF12];
+    CSRArrayOld[12'hF13] = CSRArray[12'hF13];
+    CSRArrayOld[12'hF14] = CSRArray[12'hF14];
+    CSRArrayOld[12'hF15] = CSRArray[12'hF15];
+
+    // Sstc CSRs
+    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
    
-    // PMP CFG 3A0 to 3AF
-    for(index4='h3A0; index4<='h3AF; index4++)
-        CSRArrayOld[index4] = CSRArray[index4];
-    
-    // PMP ADDR 3B0 to 3EF
-    for(index4='h3B0; index4<='h3EF; index4++)
-        CSRArrayOld[index4] = CSRArray[index4];
+    // Zkr CSRs
+    // seed not connected (015)
+
+    // extra CSRs for RV32
+    if (P.XLEN == 32) begin
+      CSRArrayOld[12'h310] = CSRArray[12'h310];
+      CSRArrayOld[12'h31A] = CSRArray[12'h31A];
+      CSRArrayOld[12'h757] = CSRArray[12'h757];
+      CSRArrayOld[12'h15D] = CSRArray[12'h15D];
+    end
  end
  
  // check for csr value change.
+  // M-mode trap CSRs
  assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0;
-  assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
-  assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
-  assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
-  assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
-  assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
-  assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
  assign CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
  assign CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
-  assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
  assign CSR_W[12'h304] = (CSRArrayOld[12'h304] != CSRArray[12'h304]) ? 1 : 0;
-  assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
-  assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
+  assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
  assign CSR_W[12'h340] = (CSRArrayOld[12'h340] != CSRArray[12'h340]) ? 1 : 0;
+  assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
  assign CSR_W[12'h342] = (CSRArrayOld[12'h342] != CSRArray[12'h342]) ? 1 : 0;
  assign CSR_W[12'h343] = (CSRArrayOld[12'h343] != CSRArray[12'h343]) ? 1 : 0;
-  assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
-  assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
-  assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
-  assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
-  assign CSR_W[12'h34A] = (CSRArrayOld[12'h34A] != CSRArray[12'h34A]) ? 1 : 0;
-  assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
-  assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
+  assign CSR_W[12'h344] = (CSRArrayOld[12'h344] != CSRArray[12'h344]) ? 1 : 0;
+
+  // S-mode trap CSRs
  assign CSR_W[12'h100] = (CSRArrayOld[12'h100] != CSRArray[12'h100]) ? 1 : 0;
  assign CSR_W[12'h104] = (CSRArrayOld[12'h104] != CSRArray[12'h104]) ? 1 : 0;
  assign CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
-  assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
-  assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
-  assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
-  assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
  assign CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
-  assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
+  assign CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
  assign CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
+  assign CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
  assign CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
-  assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
+
+  // Virtual Memory CSRs
+  assign CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
+
+  // Floating-Point CSRs
  assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
  assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
  assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
+
+  // Counters / Performance Monitoring CSRs
+  assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
+  assign CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
+  assign CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
+  // mhpmevent3-31 not connected (232-33F)
+  assign CSR_W[12'hB00] = (CSRArrayOld[12'hB00] != CSRArray[12'hB00]) ? 1 : 0;
+  assign CSR_W[12'hB02] = (CSRArrayOld[12'hB02] != CSRArray[12'hB02]) ? 1 : 0;
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign CSR_W[12'h301] = (CSRArrayOld[12'h301] != CSRArray[12'h301]) ? 1 : 0;
+  assign CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
+  assign CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
+  assign CSR_W[12'h747] = (CSRArrayOld[12'h747] != CSRArray[12'h747]) ? 1 : 0;
+  assign CSR_W[12'hF11] = (CSRArrayOld[12'hF11] != CSRArray[12'hF11]) ? 1 : 0;
+  assign CSR_W[12'hF12] = (CSRArrayOld[12'hF12] != CSRArray[12'hF12]) ? 1 : 0;
+  assign CSR_W[12'hF13] = (CSRArrayOld[12'hF13] != CSRArray[12'hF13]) ? 1 : 0;
+  assign CSR_W[12'hF14] = (CSRArrayOld[12'hF14] != CSRArray[12'hF14]) ? 1 : 0;
+  assign CSR_W[12'hF15] = (CSRArrayOld[12'hF15] != CSRArray[12'hF15]) ? 1 : 0;
+
+  // Sstc CSRs
+  assign CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
+  if (P.XLEN == 32) begin
+    assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0;
+    assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0;
+    assign CSR_W[12'h757] = (CSRArrayOld[12'h757] != CSRArray[12'h757]) ? 1 : 0;
+    assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0;
+  end
+
+
+
+  // M-mode trap CSRs
  assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300];
-  assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
-  assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
-  assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
-  assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
-  assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
  assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302];
  assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
-  assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
  assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
-  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
-  assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
-  assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
+  assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305];
  assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
+  assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341];
  assign rvvi.csr_wb[0][0][12'h342] = CSR_W[12'h342];
  assign rvvi.csr_wb[0][0][12'h343] = CSR_W[12'h343];
-  assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
-  assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
-  assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
-  assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
-  assign rvvi.csr_wb[0][0][12'h34A] = CSR_W[12'h34A];
-  assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
-  assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
+  assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
+
+  // S-mode trap CSRs
  assign rvvi.csr_wb[0][0][12'h100] = CSR_W[12'h100];
  assign rvvi.csr_wb[0][0][12'h104] = CSR_W[12'h104];
  assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
-  assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
-  assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
-  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
-  assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
  assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
-  assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
+  assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
  assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
+  assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
  assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
-  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
+
+  // Virtual Memory CSRs
+  assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
+
+  // Floating-Point CSRs
  assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
  assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
  assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];

-  assign rvvi.csr[0][0][12'h300]    = CSRArray[12'h300];
-  assign rvvi.csr[0][0][12'h310]    = CSRArray[12'h310];
-  assign rvvi.csr[0][0][12'h305]    = CSRArray[12'h305];
-  assign rvvi.csr[0][0][12'h341]    = CSRArray[12'h341];
-  assign rvvi.csr[0][0][12'h306]    = CSRArray[12'h306];
-  assign rvvi.csr[0][0][12'h320]    = CSRArray[12'h320];
-  assign rvvi.csr[0][0][12'h302]    = CSRArray[12'h302];
-  assign rvvi.csr[0][0][12'h303]    = CSRArray[12'h303];
-  assign rvvi.csr[0][0][12'h344]    = CSRArray[12'h344];
-  assign rvvi.csr[0][0][12'h304]    = CSRArray[12'h304];
-  assign rvvi.csr[0][0][12'h30A]    = CSRArray[12'h30A];
-  assign rvvi.csr[0][0][12'h301]    = CSRArray[12'h301];
-  assign rvvi.csr[0][0][12'hF14]    = CSRArray[12'hF14];
-  assign rvvi.csr[0][0][12'h340]    = CSRArray[12'h340];
-  assign rvvi.csr[0][0][12'h342]    = CSRArray[12'h342];
-  assign rvvi.csr[0][0][12'h343]    = CSRArray[12'h343];
-  assign rvvi.csr[0][0][12'hF11]    = CSRArray[12'hF11];
-  assign rvvi.csr[0][0][12'hF12]    = CSRArray[12'hF12];
-  assign rvvi.csr[0][0][12'hF13]    = CSRArray[12'hF13];
-  assign rvvi.csr[0][0][12'hF15]    = CSRArray[12'hF15];
-  assign rvvi.csr[0][0][12'h34A]    = CSRArray[12'h34A];
-  assign rvvi.csr[0][0][12'hB00]    = CSRArray[12'hB00];
-  assign rvvi.csr[0][0][12'hB02]    = CSRArray[12'hB02];
-  assign rvvi.csr[0][0][12'h100]    = CSRArray[12'h100];
-  assign rvvi.csr[0][0][12'h104]    = CSRArray[12'h104];
-  assign rvvi.csr[0][0][12'h105]    = CSRArray[12'h105];
-  assign rvvi.csr[0][0][12'h141]    = CSRArray[12'h141];
-  assign rvvi.csr[0][0][12'h106]    = CSRArray[12'h106];
-  assign rvvi.csr[0][0][12'h10A]    = CSRArray[12'h10A];
-  assign rvvi.csr[0][0][12'h180]    = CSRArray[12'h180];
-  assign rvvi.csr[0][0][12'h140]    = CSRArray[12'h140];
-  assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
-  assign rvvi.csr[0][0][12'h142]    = CSRArray[12'h142];
-  assign rvvi.csr[0][0][12'h144]    = CSRArray[12'h144];
-  assign rvvi.csr[0][0][12'h14D]    = CSRArray[12'h14D];
-  assign rvvi.csr[0][0][12'h001]    = CSRArray[12'h001];
-  assign rvvi.csr[0][0][12'h002]    = CSRArray[12'h002];
-  assign rvvi.csr[0][0][12'h003]    = CSRArray[12'h003];
+  // Counters / Performance Monitoring CSRs
+  assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306];
+  assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
+  assign rvvi.csr_wb[0][0][12'h320] = CSR_W[12'h320];
+  // mhpmevent3-31 not connected (232-33F)
+  assign rvvi.csr_wb[0][0][12'hB00] = CSR_W[12'hB00];
+  assign rvvi.csr_wb[0][0][12'hB02] = CSR_W[12'hB02];
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
+  assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
+  assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
+  assign rvvi.csr_wb[0][0][12'h747] = CSR_W[12'h747];
+  assign rvvi.csr_wb[0][0][12'hF11] = CSR_W[12'hF11];
+  assign rvvi.csr_wb[0][0][12'hF12] = CSR_W[12'hF12];
+  assign rvvi.csr_wb[0][0][12'hF13] = CSR_W[12'hF13];
+  assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
+  assign rvvi.csr_wb[0][0][12'hF15] = CSR_W[12'hF15];
+
+  // Sstc CSRs
+  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
+  if (P.XLEN == 32) begin
+    assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310];
+    assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A];
+    assign rvvi.csr_wb[0][0][12'h757] = CSR_W[12'h757];
+    assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D];
+  end
+
+
+
+// M-mode trap CSRs
+  assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300];
+  assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302];
+  assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
+  assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
+  assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305];
+  assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
+  assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341];
+  assign rvvi.csr[0][0][12'h342] = CSRArray[12'h342];
+  assign rvvi.csr[0][0][12'h343] = CSRArray[12'h343];
+  assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
+
+  // S-mode trap CSRs
+  assign rvvi.csr[0][0][12'h100] = CSRArray[12'h100];
+  assign rvvi.csr[0][0][12'h104] = CSRArray[12'h104];
+  assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
+  assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
+  assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
+  assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142];
+  assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];
+  assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144];
+
+  // Virtual Memory CSRs
+  assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
+
+  // Floating-Point CSRs
+  assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001];
+  assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002];
+  assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003];
+
+  // Counters / Performance Monitoring CSRs
+  assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306];
+  assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
+  assign rvvi.csr[0][0][12'h320] = CSRArray[12'h320];
+  // mhpmevent3-31 not connected (232-33F)
+  assign rvvi.csr[0][0][12'hB00] = CSRArray[12'hB00];
+  assign rvvi.csr[0][0][12'hB02] = CSRArray[12'hB02];
+  // mhpmcounter3-31 not connected (B03-B1F)
+  // cycle, time, instret not connected (C00-C02)
+  // hpmcounter3-31 not connected (C03-C1F)
+
+  // Machine Information Registers and Configuration CSRs
+  assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
+  assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
+  assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
+  assign rvvi.csr[0][0][12'h747] = CSRArray[12'h747];
+  assign rvvi.csr[0][0][12'hF11] = CSRArray[12'hF11];
+  assign rvvi.csr[0][0][12'hF12] = CSRArray[12'hF12];
+  assign rvvi.csr[0][0][12'hF13] = CSRArray[12'hF13];
+  assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
+  assign rvvi.csr[0][0][12'hF15] = CSRArray[12'hF15];
+
+  // Sstc CSRs
+  assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D];
+  
+  // Zkr CSRs
+  // seed not connected (015)
+
+  // extra CSRs for RV32
+  if (P.XLEN == 32) begin
+    assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310];
+    assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A];
+    assign rvvi.csr[0][0][12'h757] = CSRArray[12'h757];
+    assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D];
+  end
+
+
  // PMP CFG 3A0 to 3AF
  for(index='h3A0; index<='h3AF; index++) begin
    assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0;
@ -528,7 +675,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
    assign rvvi.csr_wb[0][0][index] = CSR_W[index];
    assign rvvi.csr[0][0][index] = CSRArray[index];  
  end
-   
+
  // *** implementation only cancel? so sc does not clear?
  assign rvvi.lrsc_cancel[0][0] = 0;

@ -554,45 +701,42 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
            $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
          end
        end
-        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
-          if(rvvi.f_wb[0][0][index2]) begin
-            $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
-          end
-        end
-        for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
-          if(rvvi.csr_wb[0][0][index2]) begin
-            $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
-          end
-        end
-        $fwrite(file, "\n");
      end
-	  if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
-		$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
-	  else if(`PRINT_MOST & !`PRINT_ALL)
-		$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", 
-		        rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
-	  else if(`PRINT_ALL) begin
-		$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", 
-				 rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
-	  	for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
-		  $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
-		end
-		for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
-		  $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
-		end
-	  end
-	  if (`PRINT_CSRS) begin
-		for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
-		  if(CSR_W[index2]) begin
-			$display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
-		  end
-		end
-	  end
-	end
+      for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+        if(rvvi.f_wb[0][0][index2]) begin
+          $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
+        end
+      end
+      for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
+        if(rvvi.csr_wb[0][0][index2]) begin
+          $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
+        end
+      end
+      $fwrite(file, "\n");
+      if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
+        $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
+      else if(`PRINT_MOST & !`PRINT_ALL)
+        $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", 
+                 rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
+      else if(`PRINT_ALL) begin
+        $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", 
+                 rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
+        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+          $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
+        end
+        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+          $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
+        end
+      end
+      if (`PRINT_CSRS) begin
+        for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
+          if(CSR_W[index2]) begin
+            $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]);
+          end
+        end
+      end
+    end
    if(HaltW) $finish;
  end
-
-
-
 endmodule

--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@ -33,12 +33,6 @@
    `include "idv/idv.svh"
 `endif

-`ifdef RVVI_COVERAGE
-    `include "RISCV_trace_data.svh"
-    `include "rvvicov.svh"
-    `include "wrapper.sv"
-`endif
-
 import cvw::*;

 module testbench;
@ -181,6 +175,7 @@ module testbench;
        "arch64zknd":    if (P.ZKND_SUPPORTED)    tests = arch64zknd;
        "arch64zkne":    if (P.ZKNE_SUPPORTED)    tests = arch64zkne;
        "arch64zknh":    if (P.ZKNH_SUPPORTED)    tests = arch64zknh;
+        "arch64pmp":     if (P.PMP_ENTRIES > 0)   tests = arch64pmp;
      endcase
    end else begin // RV32
      case (TEST)
@ -223,6 +218,8 @@ module testbench;
        "arch32zknd":    if (P.ZKND_SUPPORTED)    tests = arch32zknd;
        "arch32zkne":    if (P.ZKNE_SUPPORTED)    tests = arch32zkne;
        "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
+        "arch32pmp":     if (P.PMP_ENTRIES > 0)   tests = arch32pmp;
+        "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
      endcase
    end
    if (tests.size() == 0 & ElfFile == "none") begin
@ -570,7 +567,7 @@ module testbench;
  assign SPIIn = 1'b0;

  if(P.EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
+    ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE))
    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
  end else begin
@ -973,12 +970,6 @@ test_pmp_coverage #(P) pmp_inst(clk);
  /* verilator lint_on WIDTHTRUNC */
  /* verilator lint_on WIDTHEXPAND */

-`ifdef RVVI_COVERAGE
-    rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
-    wallyTracer #(P) wallyTracer(rvvi);
-    wrapper #(P) wrap(clk);
-`endif
-
 endmodule

 /* verilator lint_on STMTDLY */
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{
  "rv32i_m/privilege/src/WALLY-lrsc-01.S"
 };

+string arch32pmp[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/pmp32/src/pmp-CFG-reg.S",
+  "rv32i_m/pmp32/src/pmp-CSR-access.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RWX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X.S"
+};
+
+string arch64pmp[] = '{
+  `RISCVARCHTEST,
+  "rv64i_m/pmp64/pmp64-CFG-reg.S",
+  "rv64i_m/pmp64/pmp64-CSR-access.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-R.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW.S",
+  "rv64i_m/pmp64/pmp64-NA4-RWX.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-X.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RWX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-R.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW.S",
+  "rv64i_m/pmp64/pmp64-TOR-RWX.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-X.S"
+};
+
+string arch32vm_sv32[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
+};
+
 string arch64priv[] = '{
  `RISCVARCHTEST,
  "rv64i_m/privilege/src/ebreak.S",
--- a/tests/coverage/ifu.S
+++ b/tests/coverage/ifu.S
@ -50,6 +50,11 @@ main:
    c.sb s1, 0(s0)    // exercise c.sb
    c.sh s1, 0(s0)    // exercise c.sh

+    .hword 0x2005      // line 110
+    .hword 0x6101      // line 114
+    .hword 0x6201      // line 115
+    .hword 0x0202      // Illegal compressed instruction with op = 10, Instr[15:13] = 000, c.slli x4, 0. Line 151 illegal instruction
+    .hword 0x4002      // Illegal compressed instruction with op = 10, Instr[15:13] = 010, c.lwsp zero, 0. Line 158 illegal instruction
    .hword 0x8C44      // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
    .hword 0x9C00      // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction

--- a/tests/custom/crt0/pre_main.c
+++ b/tests/custom/crt0/pre_main.c
@ -2,6 +2,8 @@

 #include "pcnt_driver.h"

+extern int main(int argc, char *argv[]);
+
 int pre_main(int argc, char *argv[]) {
  long int bpmp0, brcnt0, bpmp1, brcnt1;
  long int bpmp_diff, brcnt_diff;
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate):
        ispec = utils.load_yaml(isa_yaml)['hart0']
        self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
        self.isa = 'rv' + self.xlen
-        self.sailargs = ' '
+        self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
        self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
        if "I" in ispec["ISA"]:
            self.isa += 'i'
@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate):

            execute = "@cd "+testentry['work_dir']+";"

-#            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
            cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
            compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
            execute+=compile_cmd+";"
@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate):
                reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
            else:
-                execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
-#                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step  ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)

            cov_str = ' '
            for label in testentry['coverage_labels']:
--- a/tests/riscof/spike/spike_rv32gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32gc_isa.yaml
@ -26,4 +26,4 @@ hart0:
              legal:
                - extensions[25:0] bitmask [0x000112D, 0x0000000]
              wr_illegal:
-                - Unchangedcd 
+                - Unchanged
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@ -133,8 +133,8 @@ cause_m_time_interrupt:
    add t3, t2, t3       // add desired offset to the current time
    bgtu t3, t2, nowrap_m  // check new time exceeds current time (no wraparound)
    addi t6, t6, 1       // if wrap, increment most significant word
-    sw t6,4(t4)          // store into most significant word of MTIMECMP
 nowrap_m:
+    sw t6,4(t4)          // store into most significant word of MTIMECMP
    sw t3, 0(t4)         // store into least significant word of MTIMECMP
 time_loop_m:
    addi a3, a3, -1
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
@ -36,20 +36,20 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources

 // Code copied from test library to cause m time interrupt, with time loop replaced with wfi.

-/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi 
+/* Note: the following line might cause problems in the future. If more than 0x100 cycles are needed before the wfi 
 instruction begins, then the program might fall into a loop and run forever*/
-li x28, 0x50          // Desired offset from the present time
-mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
-la x29, 0x02004000    // MTIMECMP register in CLINT
-la x30, 0x0200BFF8    // MTIME register in CLINT
-lw x7, 0(x30)         // low word of MTIME
-lw x31, 4(x30)         // high word of MTIME
-add x28, x7, x28       // add desired offset to the current time
-bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-addi x31, x31, 1       // if wrap, increment most significant word
-sw x31,4(x29)          // store into most significant word of MTIMECMP
+    li x28, 0x100          // Desired offset from the present time
+    mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    la x30, 0x0200BFF8    // MTIME register in CLINT
+    lw x7, 0(x30)         // low word of MTIME
+    lw x31, 4(x30)         // high word of MTIME
+    add x28, x7, x28       // add desired offset to the current time
+    bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+    addi x31, x31, 1       // if wrap, increment most significant word

 nowrap:
+    sw x31,4(x29)          // store into most significant word of MTIMECMP
    sw x28, 0(x29)         // store into least significant word of MTIMECMP

 auipc ra, 0x0
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@ -136,8 +136,8 @@ cause_m_time_interrupt:
    add t3, t2, t3       // add desired offset to the current time
    bgtu t3, t2, nowrap_m  // check new time exceeds current time (no wraparound)
    addi t6, t6, 1       // if wrap, increment most significant word
-    sw t6,4(t4)          // store into most significant word of MTIMECMP
 nowrap_m:
+    sw t6,4(t4)          // store into most significant word of MTIMECMP
    sw t3, 0(t4)         // store into least significant word of MTIMECMP
 time_loop_m:
    addi a3, a3, -1
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
@ -35,30 +35,24 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources

 // Code copied from test library to cause m time interrupt, with time loop replaced with wfi.

-li x28, 0x60          // Desired offset from the present time
-mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
-la x29, 0x02004000    // MTIMECMP register in CLINT
-la x30, 0x0200BFF8    // MTIME register in CLINT
-lw x7, 0(x30)         // low word of MTIME
-lw x31, 4(x30)         // high word of MTIME
-add x28, x7, x28       // add desired offset to the current time
-bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-addi x31, x31, 1       // if wrap, increment most significant word
-sw x31,4(x29)          // store into most significant word of MTIMECMP
+    li x28, 0x60          // Desired offset from the present time
+    mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    la x30, 0x0200BFF8    // MTIME register in CLINT
+    ld x7, 0(x30)         // read MTIME
+    add x28, x7, x28      // add offset
+    sw x28, 0(x29)        // MTIMECMP = MTIME + offset

-nowrap:
-    sw x28, 0(x29)         // store into least significant word of MTIMECMP
+    auipc ra, 0x0
+    addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt

-auipc ra, 0x0
-addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt
+    wfi // test wfi until trap goes off

-wfi // test wfi until trap goes off
-
-li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off.
-// this tests whether wfi is a nop or not since we should get the output for the interrupt before this one
-sd x28, 0(x6)
-addi x6, x6, 8
-addi x16, x16, 8
+    li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off.
+    // this tests whether wfi is a nop or not since we should get the output for the interrupt before this one
+    sd x28, 0(x6)
+    addi x6, x6, 8
+    addi x16, x16, 8

 END_TESTS
				`@ -1 +0,0 @@`
				`Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31`