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Added SystemVerilog flag to fma.do so that fma16 compiles properly
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@ -8,7 +8,7 @@ onbreak {resume}
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# create library
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# create library
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vlib worklib
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vlib worklib
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vlog -lint -work worklib fma16.v testbench.v
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vlog -lint -sv -work worklib fma16.v testbench.v
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vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
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vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
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vsim -lib worklib testbenchopt
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vsim -lib worklib testbenchopt
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